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Project: Pipelined Architecture Assembly Code and Simulation
In this project you will design a simple assembly language interpreter for a 5 stage pipelined CPU with a data cache.
Registers and Memory
The CPU contains 32 registers with names R0…R31. Register R0 will always contain value 0. There are also memory locations denoted M[A], where A is a memory address.
In the assembly program there are special statements for data initialization and also for printing the contents of the registers and memory.
Data initialization statements for the registers is of the form Ri = X, where register Ri gets value X. You can also assign ranges of values, as for example Ri-Rj = X, where j>i, such that all registers from Ri to Rj get value X. For memory we gave data initialization of the form M[A] = X, which assigns value X to memory location A. We also have range memory allocations of the form M[A-B] = X, where A>B, such that the memory contents from M[A] to M[B] get value X. Examples:
R5 = X //register R5 gets value X
R5-R20 = X //all registers between R5 to R20 get value X
M = 50 //memory location 100 gets value 50
M[25-30] = X //all memory locations between addresses 25 to 30 get value X
Assume that initially all registers and all memory locations contain value 0.
For printing the contents of the registers we have instructions of the form PRINT Ri, which prints the contents of register Ri. We can also print the contents of ranges of registers with instructions of the form PRINT Ri-Rj, which prints the contents of all memory registers from Ri to Rj. Similarly for memory, we have initialization instructions of the form PRINT M[A] which prints the contents of memory location A. We can also print the contents of a range of memory locations, as for example PRINT M[A-B], which prints the contents of all memory locations between A to B. Examples:
PRINT R1 //prints the contents of R1
Sample output: R1:10