ASIC Design & Verification Interview Panel required urgently

Avg Bid (INR)
750 / hr
Project Budget (INR)
₹400 - ₹750 / hr

Project Description:
Bachelors in Engineering from a reputed institute with good academic record
Having 6+ years experience in ASIC design & verification
Good Knowledge on Tools like VMM, UVM, OVM, VERA Preferable SOC Verification.
ASIC design experience with RTL coding in Verilog/VHDL, FPGA experience, FPGA Board bring, FPGA synthesis

Hours of work: Unspecified Project Duration: Ongoing Skills required:
C Programming, Embedded Software, RTOS, Verilog / VHDL
About the employer:
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