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I have a design based on the 144 pin Altera Cyclone EP3C25.
I programmed a NIOS II processor with external SRAM connected to the FPGA but for this I need more than 30-pins.
In order to reduce this amount I found an EDN article in which is descibed how to multiplex the data-lines with the lower address-lines.
I have attached this article (Look for: SDRAM interface slashes pin count).
Is need someone who can change the nios32_sdram.v which is generated by the MegaWizard Plug-In Manager according to the above article.