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This is a very very small project. Won't take much time because all design code is already written.
I already have a code. you need to fix some errors in verilog and write 2-3 testbenches and make already written code working (verification should not fail).
More than verilog design, main work is test bench. You should be expert.
Not for someone who want to learn. project should be completed in a day. Not apply if you are not free next 2 days.
Please send me message with your experience with verilog, previous verilog projects and education.
I will send you exact details about project in message.
You should know about computer architecture, pipelining.
Actually very simple project. 90% work is done. Budget no more than $50. will give bonus if everything completed on time.