# Digital Logic Design Project

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Bids
5
Avg Bid (USD)
\$35
Project Budget (USD)
\$30 - \$30

Project Description:
I have what should be a very easy Digital Logic and Design project that I need done. I have recently changed majors from EE to ME and no longer need the class for which this project is for, however I still need to make a decent grade so that it doesnt pull down my gpa. My teacher is horrible and has not done a very good job at teaching this subject. I have listed below the requirements for the project and would love for someone to throw this together for me by Nov 28th. I am a college student and can only afford the meager \$30. I feel that someone with experience and knowledge on the subject could pull this together rather effortlessly. Listed below are the requirements for the project. It only has to be written on paper and is not very demanding.

You are to design a controller for an automatic paint color-matching system. Your circuit will get a signal READY when the first of 4 6-bit words is available. READY is always 1 for only ONE clock pulse. Each 6-bit word is divided into 2 parts. The lower 4 bits give the amount of color to be added to the base paint. The upper 2 bits give the color: Blue(00), Yellow(01), Red(10), Black(11). You should save each of these numbers. Wait for another READY signal, which will give you a 2 bit word (the upper 2-bits of the data in lines) telling the color, and on the next clock pulse, decrement the appropriate count by one, and make the output SQUIRT 1 for four clock pulses. With each READY decrement the selected counter. (The READY signals will be spaced by more than 4 clock pulses.) When ALL counters are ZERO, send an output DONE.
As usual DO NOT GATE THE CLOCK ANYWHERE. The circuit must be synchronous.

Some notes of importance, the following should be included.
State Diagram
State Tables
Explain in detail how it works
When using MUX and counters, explain
MSI: counters,MUX, give function tables (no innards)

Skills required:
Education & Tutoring, Electrical Engineering, Electronics, Engineering
Project ID: 3684557
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