Field Programmable Gate Array Implementation of Reed-Solomon

Avg Bid (INR)
Project Budget (INR)
₹1500 - ₹12500

Project Description:
Abstract—This paper demonstrates an FPGA implementation
of the Reed-Solomon, RS(255,239), codec architecture for the
OTN G.709. The RS codec is designed to occupy the least
amount of logic blocks, be fast and parameterizable. I am
presenting an efficient implementation of the encoder algorithm
on reconfigurable devices in addition to a non-finalized version
of the decoder. Both encoder and decoder are synthesized to
Altera’s StratixII and benchmarks are run against Altera’s Reed
Solomon Code. Xelic’s encoder is measured to be about half the
size of Altera’s encoder. Effort on optimizing Xelic’s decoder is
underway to have an efficient implementation of the decoder

Skills required:
Marketing, Verilog / VHDL
About the employer:
Public Clarification Board
Bids are hidden by the project creator. Log in as the employer to view bids or to bid on this project.
You will not be able to bid on this project if you are not qualified in one of the job categories. To see your qualifications click here.

₹ 12500
in 18 days
Hire scs9gp
₹ 1900
in 18 days
Hire mehedibd85
₹ 10500
in 15 days
Hire uzairsaeed702
₹ 1900
in 20 days
Hire effiworker
₹ 9000
in 45 days