Hi, I'm interested in undertaking your project. I am a professional RTL engineer using Verilog HDL and VHDL for over 15 years. I have designed multiple complete and partial CPU soft-core designs in the past, like DLX and MIPS-I/R3000 clones as well as my own in-house ASIPs (Application-Specific Instruction-set Processors). Regarding my portfolio you can look for ByoRISC, YARDstick custom instruction generation framework and HercuLeS high-level synthesis in the web.
Thank you in advance!