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FPGA Verilog design
We have a Spartan 3E FPGA PCB which takes in 8 channels of analog signals and sends them to a laptop using 10M ethernet UDP. The signalling is all done in the FPGA including ARP and UDP layers. A static IP address is used. Even the front end signal generation and reception is done by bitbashing in the FPGA.
There are also other timing controls set up from the laptop, also via UDP. These include serial DACs and ADCs and other internal controls.
We will design and build the PCB, load the code and test it.
Identification of a suitable 100M Phy device for production hardware.
Port of the FPGA’s ARP and UDP layers to the new Phy interface. The current FPGA code in written in Verilog.
Change the timing controls from 8 channels to 1 channel use.
The pinout of the FPGA will be defined and used for the PCB layout.
Windows C# software
The control and display of the data from the FPGA PCB is done on a laptop or tablet with Windows 7 or 8. The control commands and data are sent and received via the Ethernet or WiFi port using UDP. The data can be displayed in different ways, as a wiggle trace or a scrolling greyscale plot. The data is stored on a selected storage device and can also be replayed.
We have the software for the 8 channel control version and want to modify it to a single channel version.