FPGA verilog project
Project ID:
784771Project Type:
FixedBudget:
$750-$1500 USD
Project Description:
Verilog design and testing skillsSkills required:
Algorithm, C++ Programming, Testing / QA, Verilog / VHDL
Public Clarification Board
4 messages
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nadir1986
I am interested in this project and Can you give me some more details about the project. I am well experienced with the tools like Matlab, Xilinx, Modelsim, Cadence, Quartus II and FPGA technologies especially from Altera and Xilinx. I have strong knowledge and experience with RTL development, full chip level synthesis and timing analysis. I have the ability to experiment with design for area reduction and better timing closure and resolve warnings / errors reported during synthesis.
over 1 year ago
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iBiuz
Can you give some details about the language, the platform, the project, etc...
over 1 year ago
Awarded Bids
All Bids ()
nityendrasingh
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nityendrasingh
From India
Offline
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General Freelancer Orientation (75%, 81st percentile)
Foundation EUFreelance.com Member
$900
in 10 days
$450 Milestone Requested
$450 Milestone Requested
over 1 year ago
please give me a chance to do it
manoharkalyan
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manoharkalyan
From United States
Offline
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$750
in 20 days
$75 Milestone Requested
$75 Milestone Requested
over 1 year ago
I have a very good experience in working with Verilog and FPGAs. I have done a lot of projects in those fields.
I have two years experience in FPGA design and simulation by using Altera and Modelsim tools, respectively
asicdsm
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asicdsm
From Spain
Offline
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Foundation EUFreelance.com Member
$5000
in 0 days
over 1 year ago
Please see your PM
Hi, I have more than 5 years FPGA/Verilog/VHDL hands-on experience. Have applied FPGA technology to telecommunication, video processing and industry control field in both IP and system level. Hope I can win this bid.
VasileToma
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VasileToma
From Romania
Offline
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$1200
in 10 days
$240 Milestone Requested
$240 Milestone Requested
over 1 year ago
Hello sir, I am opened for discussion and negotiation regarding this project. I offer you my experience which consists of 4 years of ASIC & FPGA designs. I have work experience in almost all of the stages of the im... more
Hello sir, I am opened for discussion and negotiation regarding this project. I offer you my experience which consists of 4 years of ASIC & FPGA designs. I have work experience in almost all of the stages of the implementation flow for both ASIC and FPGA (RTL coding in Verilog/System Verilog or VHDL, behavioral and gate-level simulation, static timing analysis and optimization, place & rout optimizations, DFT, etc...). Besides I have hands-on experience in areas as video processing, DSP, and mixed-signal designs. For projects with a higher complexity I can bring in between 2-4 peoples with the same amount of experience.
Regards
Vasile T. less
I am well experienced in Verilog and VHDL coding. I had developed several codes on the xilinx board. Please provide more details regarding the project.Please give me a chance to do this project.
uzairsaeed702
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uzairsaeed702
From Germany
Offline
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$900
in 2 days
$315 Milestone Requested
$315 Milestone Requested
over 1 year ago
Sir please Give me chance to do that i have Currently Developed and Architecture which is in process of ASIC design
Please see PM
Hi, I have interest on this project. Please check your PMB.
Bid and timeframe depend on the project. 30 days is the maximum
Please check PMB
Dear,sir.
Can do it for you.
Please check pmb.Thank you.
Hi, I have 3 years of experience designing models for FPGA implementation. I have worked on my last year of college with XILINX and MODELSIM. Id interested, please send me more details.
Hi! I have three years experience in vhdl and verilog designing and I did a one year course of such a project in my last year of Electrical Engineering of bachelors. I'll provide you a sample of my project in a day or ... more
Hi! I have three years experience in vhdl and verilog designing and I did a one year course of such a project in my last year of Electrical Engineering of bachelors. I'll provide you a sample of my project in a day or two. Thank you. less