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Matlab codes porting to FPGA

Bids 
16
Avg Bid
$2003 USD
CLOSED

  • Project ID:

    723941

  • Project Type:

    Fixed

  • Budget:

    $250-$750 USD

Project Description:

The FPGA project is to porting a WLAN’s PHY cores into a Xilinx FPGA development board (E.g Spartan 3A). Use of the public domain WLAN’s PHY cores from Rice University’s WARP project (http://warp.rice.edu/trac/wiki/OFDMReferenceDesign/Changelog), the cores (Matlab Simulink’s mdl files) porting into a Xilinx FPGA development board. We recommend to goto the rice.edu link (above), download the matlab files, and try out yourself first before your bid.

Details Project Tasks are followings;

• Break the WARP’s Simulink’s mdl files into transmitter (Tx) and receiver (Rx) parts (currently, the WARP mdl files are combined) because the core logics are too big for the Spartan3A chip, and port the each part into a Xilinx’s Spartan3A-DSP board.
• Perform a slight modification and adding for the WARP mdl files to fit the board and demonstration (will be discussed later).
• The Xilinx’s Spartan3A-DSP board is combined with a P160 Analog-to-Digital daughter card (ADC/DAC) by Avnet. The WARP Simulink mdl and P160 ADC Simulink mdl files are need to integrate together for TX and RX.
• A simple Matlab GUI will design for configure and run the board.

Qualifications for this project;

• Must familiar with Xilinx FPGA design tools including System Generator, and required experience for porting/debug on various Xilinx development boards.
• Must familiar with Matlab and Simulink
• Must familiar with WLAN technology (OFDM modulation/demodulation), DSP
• Experience on DSO, Spectrum analyzer, ADC/DAC board, hands-on digital signal processing, and data analysis.

If you are interested to submit this project, we encourage to download the WARP project and try first before you bid. And submit precise technical details that how you can divide the cores into TX/RX. And expect to have multiple technical discussions before we finalize the project contract.

Skills required:

Electronics, Engineering, Matlab & Mathematica, Verilog / VHDL, Wireless
See more: matlab fpga, fpga matlab, adc system generator, matlab codes, porting matlab dsp fpga, simulink mdl matlab fpga, fpga development board matlab, p160 dsp simulink, matlab fpga board, warp adc system generator, matlab fpga project, fpga matlab edu, design receiver porting fpga, matlab spartan, porting technology fpga, fpga porting, run matlab files fpga, matlab codes fpga, matlab mdl, rice university fpga board, ofdm system generator fpga, card generator, spartan simple project, xilinx system generator, matlab processing

Project posted by:

dewimoon United States
(0 Reviews)
Last seen:
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Public Clarification Board

5 messages

  • owncoder

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    over 1 year ago

  • engrshahid

    Hi
    I am an Electrical engr having MS in Electronics engineering. I have 4 international research papers in which 2 are on DSP & FPGAs. One of my published research paper is attached here as sample.I can do this project

    Attachment: Research%2520paper_by_Shahid%5B1%5D.doc

    over 1 year ago

  • rem1234

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    over 1 year ago

  • ugmadhu

    I am eagerly looking forward for the technical discussions with you and also about your project requirements.

    over 1 year ago

  • ugmadhu

    I am UGMADHU from UG Consultants, Bangalore, India. I am quite passionate about the DSP concepts and implementation using MATLAB and SIMULINK tools. I am very confident that I can take up this project and finish the project with utmost efficiency and provide you with high performance giving implementation.

    To talk about me further, I am training consultant regulerly providing corporate training in many companies on the topic "DSP using MATLAB"

    over 1 year ago


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All Bids ()

Freelancers Msg Bid (USD) Time of Bid Reputation
vedenev Russian Federation
vedenev
Russian Federation From Russian Federation     Offline
$1500 in 30 days 
0
over 1 year ago
5.0
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4 Reviews
71% Completion Rate
I am professional matlab programer: http://simulations.narod.ru/

bchandra1955 India
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bchandra1955
India From India     Gold Member     Offline
  General Freelancer Orientation (75%, 81st percentile)
  Foundation EUFreelance.com Member
$1500 in 150 days 
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over 1 year ago
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I am automation domain expert ( see profile), and I am supported by two electronics engineers with 20 years of experience. I have seen the reffered site and downloaded the required materuial.Discus. Regards, Brajesh

mastermatlab Jordan
mastermatlab
Jordan From Jordan     Offline
$700 in 10 days 
0
over 1 year ago
4.2
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4 Reviews
75% Completion Rate
hi i am ready to this project, if you want more information we can chat here

AHSolution Egypt
AHSolution
Egypt From Egypt     Offline
  Foundation EUFreelance.com Member
$1600 in 60 days 
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over 1 year ago
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New Freelancer!
Experienced Digital Design Engineer, please check PM.

joemwalter United States
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joemwalter
United States From United States     Offline
$19200 in 90 days 
$1920 Milestone Requested
over 1 year ago
0.0
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New Freelancer!
I can do this, but to do it right would require two months of work. 320 hours at $60/hr = $19,200 I am still most interested in this project.

zealing United States
zealing
United States From United States     Offline
$700 in 30 days 
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over 1 year ago
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EEDesigner Pakistan
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EEDesigner
Pakistan From Pakistan     Offline
$1000 in 60 days 
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raji2010 India
raji2010
India From India     Offline
$250 in 90 days 
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over 1 year ago
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My skill set involves Verilog , VHDL with 36 months experience. I am familiar with the internal working of SPARTAN generation FPGAs. I have implemented control logic for IO transition board in Mission Computer to be fi... more
My skill set involves Verilog , VHDL with 36 months experience. I am familiar with the internal working of SPARTAN generation FPGAs. I have implemented control logic for IO transition board in Mission Computer to be fitted in fighter aircraft. less

ftajer Iran
ftajer
Iran From Iran     Offline
$500 in 20 days 
$50 Milestone Requested
over 1 year ago
0.0
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i am ready to do

maior India
maior
India From India     Offline
$650 in 7 days 
$325 Milestone Requested
over 1 year ago
0.0
0.0
0 Reviews
New Freelancer!
HI, I have 7+ years experience in FPGA design activities. Do contact me if you are interested with my bidding. My Mail: vlsi dot solution at gmail.com

nicolasherve Brazil
nicolasherve
Brazil From Brazil     Offline
$750 in 60 days 
$15 Milestone Requested
over 1 year ago
0.0
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see PM please.

engrshahid Pakistan
engrshahid
Pakistan From Pakistan     Offline
$600 in 30 days 
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over 1 year ago
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Hi I am an electrical engineer have good hands in Matlab & Verilog, Plz see the personal message.

shreyfreelancer United States
shreyfreelancer
United States From United States     Offline
$700 in 30 days 
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over 1 year ago
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chinnisudha India
chinnisudha
India From India     Offline
$700 in 75 days 
$140 Milestone Requested
over 1 year ago
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Hi, I'd done few of projects on xilinix FPGA's and CPLD's. I have experience on DSP and VLSI. let me know your queries for clarification.

moodz Australia
moodz
Australia From Australia     Offline
$500 in 30 days 
0
over 1 year ago
0.0
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New Freelancer!
I propose that trying to port the WARP HDL code to the spartan 3 series is a waste of time as there is no PPC CPU in these FPGAs. The outcome can be delivered by delivering a SOC 'system on chip' solution that pretty m... more
I propose that trying to port the WARP HDL code to the spartan 3 series is a waste of time as there is no PPC CPU in these FPGAs. The outcome can be delivered by delivering a SOC 'system on chip' solution that pretty much already exists. MIPs RISC cpu with LWIP eth interface. 4M flash, 16M DDR ram, VGA with text console and multichannel waveform display for examining DSP results. Fits easily in a Spartan 3e500 or Spartan 3A 400. Up to you. less

satinwood China
satinwood
China From China     Offline
$1200 in 30 days 
$600 Milestone Requested
over 1 year ago
0.0
0.0
0 Reviews
New Freelancer!
I have over 10 years experience in FPGA design. I can deliver the project on time. But before start a success FPGA porting, we must clarify sevearl key questions. 1, Please speicfy which FPGA develop broad is target.... more
I have over 10 years experience in FPGA design. I can deliver the project on time. But before start a success FPGA porting, we must clarify sevearl key questions. 1, Please speicfy which FPGA develop broad is target. E.g which device, its capacity, IO, etc. 2, What is the working frequencing. 33M hz, 100M hz? 3, Which day is the deadline? 4, Have you done some basic estimation on Resouce usage, DSP count, RAM counts? If you have a compile result of RX/TX combined version, please share the log of System Generator to me. Area/Timing reports are also required. Only those questions got answered, we can do serious BID. Thanks. --Leon  less

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