Freelancer
IC Layout engineers
IC Layout engineers is project number 744800
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Status:
Frozen
(Bid period finished)
Selected Providers: -
Budget: $250-750
Created: 07/21/2010 at 9:10 EDT
Bid Count: 9
Average Bid:
$ 6936
Ends: 08/10/2010 at 9:10 EDT
Project Creator:
amitj9
Employer Rating: (No Feedback Yet)
Description
|
IC layout project for 9-12 months on contract basis People bidding should be experienced in backend, layout, Cadence Virtuoso, memory compilers Description : Memory Compiler Engineer to help develop and validate high performance CMOS SRAM embedded memory compilers. Will develop compiler modules for CMOS SRAM memories, including physical tiling, netlist generation, timing analysis and front end model generation. Should be experienced with circuit design, IC layout, unix scripts, and CAD verification. Should have at least 2 years experience in memory or IC design, preferably memory, and at least a Diploma/BS in engineering. Interested bidders should send their resume along with the bid. Regards, Design Labs world wide web dot designlabsindia dot com |
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