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ahmedmohamed85

FPGA expert

Username: ahmedmohamed85

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Location: cairo, Egypt

Member since: January 2012

Reputation:

5.0/5

(75 reviews)

6.6
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7 users have recommended this freelancer.

My projects:

  • $300 USD
    5.0
    Profile image for Seller client12345

    client12345

    6 days ago

    excellent work!!

    Project Description:the details of this project will be available upon request. This is very important for me, and I need a contractor who is very knowledgeable with verilog
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  • $90 USD
    5.0
    Profile image for Seller cronicksr2

    cronicksr2

    Mar 4, 2014

    Finished early and did a great job!

    Project Description:Design and simulate an 8-bit adder/subtractor using a hierarchical Verilog structural description. The design should accept two two's complement 8-bit inputs (x and y) and generate an output (result) which is either their sum or difference based on another input (sub)...
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  • $459 USD
    5.0
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    Alain1234

    Mar 1, 2014

    He is the best freelancer I have ever deal with and he can provide the solution on time and he is excellent on communication.I recommended him for anybody who want the best freelancer.

    Project Description:Overview • The Design Task is the systems design and test of a prototype Serial Data Packet System. • The system will be developed as a VHDL model using Xilinx ISE WebPack Version 14.5 that includes the use of the Xilinx iSim simulation tools for design verification...
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  • $500 USD
    5.0
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    client12345

    Feb 26, 2014

    works fast and very efficently!!!!

    Project Description:the details of the project are reserve to this freelancer
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  • $250 USD
    5.0
    Profile image for Seller jimmyp80

    jimmyp80

    Feb 24, 2014

    Amazing work ethic. He will get the job done. Many thanks my friend

    Project Description:I need a CPU to be designed in system verilog. A diagram of the CPU is already provided. All necessary files will be given. I need this to be done ASAP and I need to be sure that you can do it. You can...
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  • $277 USD
    5.0
    Profile image for Seller abdrazagmohAbdo

    abdrazagmohAbdo

    Feb 12, 2014

    I am very happy to work with him

    Project Description:This is a school assignment that requires us to design a simple 5-stage pipeline CPU. It should be able to detect data hazard and insert bubbles into the pipeline accordingly. This is the description...
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  • $250 USD
    5.0
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    client12345

    Feb 9, 2014

    a job well done!!!!

    Project Description:the details of the project are reserve to this freelancer
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  • $300 USD
    5.0
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    client12345

    Feb 5, 2014

    he is really good at vhdl

    Project Description:N/A
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  • $150 USD
    5.0
    Profile image for Seller CoachingPNL

    CoachingPNL

    Feb 4, 2014

    Perfect. Five Stars, Ahmed an excellent job like a PRO, with a very good support ans comunication. Thank you Ahmed

    Project Description:I need VHDL code and all testbench files for a digital clock. Should appear on the LCD: Line 1: HH: MM: SS Line 2: Watch NLP Other Information Hours (HH) 00 to 23 With the possibility do set...
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  • $175 USD
    5.0
    Profile image for Seller venossuc

    venossuc

    Jan 30, 2014

    Mr Ahmad is very a qualified helpfull freelancer. He has really an excellent knowledge in the theory, and an excellent experince in project's implementation.I recommend him as the best.<br/>

    Project Description:Hallo, iam a student in electronic`s Faculty, familiar with assembly, logic bases. i am learning now the bases of FPGa, VERILOG, VHDL i am looking for a very expert person in FPGA to teach me a course in FPGA...
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    ahmedmohamed85 has not completed any projects.
  • $333 USD In Progress

    The aim of this is to design, simulate and synthesise an 8 bit x 8 bit signed number multiplier based upon a simple parallel Braun multiplier, see figure 1 which shows a 5 bit x 5 bit multiplier as an example. You will use the Xilinx design software 14.7 in order to achieve your aims.(VHDL, Testbench and simulations). the design of this needs to be in behavioral only.please see attachment for further details

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  • $50 USD/hr In Progress

    An algorithm must be done using vhdlthe details will be given in person

  • £35 GBP/hr In Progress

    Implement a Serdes a full duplex communication system between two microcontrollers, with 16 datablock buffering. The Serdes implemenation will also include auto sync lock. Data will be passed in 16 byte blocks, with interface to the microcontollers being 16 bit

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  • $35 USD/hr In Progress

    Hi ahmedmohamed85, I noticed your profile and would like to offer you my project. Please review the project description and we can discuss any details.

  • $50 USD/hr In Progress

    encryption is done by 1 of to types of ciphersblock ciphers or stream ciphersto increase complixty and security we will use both typesthis means data will be encrypted using block cipherand the result cipher txt will be encrypted using stream ciphertherfore 2 ciphers will be usedwith 2 different key with 2 different keywich result in a highly encrypted datato decrypt this data we need to decrypt it using stream cipherthen decrypt the result using block cipherthe challange is to make a high performance designto encrypt data using 2 ciphersin small timemeans with high speed

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  • €611 EUR In Progress

    ALL FILES ARE ATTACHEDEssay Language : EnglishDissertation ChapterSize : 80 pagesDeadline : 07/11/2013Faculty: : Electronics and Computer EngineeringEssay Tittle : Development of the WebP image compression algorithm in an FPGA as embedded systemSubject Title : Embedded systemsDetails : The development must be done using the VHDL programming language and fully functional in Xilinx FPGA platforms, such as Spartan, Virtex, Zinq, using the Xilinx IDE and EDK suit. It should be fully developed for parallel process of data. Speed measurement and comparison to the JPEG standard for size and compression speed. Required Block diagram, Development process and Code (not counted in pages).

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  • $555 USD In Progress

    It has to be created in fpga technology.create 32-bit cpu of global purpose, specification is adjusted arm architecture. cpu is RISC architecture with: registry file, load/store architecture, addressing is based on values in registries and in instruction, instruction word is 32 bit, conditional execution of most instruction.cpu has pipeline. hazards need to be resolved with hardware.etc...Needed:- vhdl code for that processor- tests and vhdl testbench code- documentation

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  • $125 USD Yesterday

    Design, simulate and implement a simple UART based on a 16550 UART model using the Altera’s DE-II Educational Board.Description: Your UART should have the following modules (but not limited to):•UART Transmitter•UART Receiver•Clock Division Module for generating a different receiver clock that is half of the transmitter clock (For example, if the transmitter is accepting data at 10 Hertz then the receiver must receive the data at 5 Hertz).Note: Use the same DE-II board as both Transmitter and Receiver, each having 8X8 byte FIFOs and these should be buffered similar to the USRT that you designed in the previous lab.

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  • $1500 AUD 4 days ago

    Create a specific 8051 soft core processor in Verilog for Spartan-3E FPGA. Details to follow if you are interested and able to assist.

  • $35 USD/hr 5 days ago

    i am making now iphone application want to control TV screen to display some tables for stock market and i want u help me for make interfaceif u interest pls contact me if u have viber my number is 0128126884 also wahatsappbest regards

    [more]
  • $2222 USD 25 days ago

    You must integrate and interface a CMOS sensor from either OmniVision or Aptina, of a minimum of 5MP. The FPGA must support all sensor controls, resolution and fps; and have a interface for said controls on a embedded web server on the FPGA. The FPGA must support TCP/IP and stream the video in a webserver. FPGA can be a SPARTAN 3E or other lower cost FPGA.

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  • $333 USD 28 days ago

    The Alarm System is monitoring one door, two windows and smoke sensor. -The Alarm can be armed by pushing one arm button.-Once armed, if one or more sensor is triggered then an alarm will sound-A six bit code holds a holds sequence of bits to disarm the system.-The Six bit sequence is read by hitting a disarm button-If the six bit sequence entered wrong three times then siren will sound. If right the alarm will disarm.-At anytime, (Armed or not Armed) alarm will sound if smoke sensor is triggered.-A led will turned on if Alarm is armed.Determine Circuit inputs and outputs.Draw state flow diagramCreate state tableMinimize your statesPerform state assignmentsWrite VHDL code using QuartusII software.Compile and Simulate each scenario and situation and explain on the simulation caption your inputs outputs and behavior. Write a detailed report that include Goal, design procedure, steps taken, problems faced, solutions, simulation results and a conclusion.Create a PP presentation.Extra points: Implement a delay from the time the arm button is pushed to the time systems get armed. This will allow the user to hit the arm button and exist/get out of the place.

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  • $388 USD 28 days ago

    Verilog programmer for device to encrypt and decrypt voice

  • £150 GBP Mar 22, 2014

    Hello,\r\n\r\nI am looking for somebody who is a professional in VHDL programming \r\ni need a code that VHDL code that receives decimal value\r\n\r\nthank you

  • $15 USD/hr Mar 20, 2014

    We are planing to create an energy meter (or analyzer) which should be capable of measuring active, reactive and apparent energy in a power line system using Rogowski coil, current transformer and shunt sensors. The data will be sent our gateway by using RS 485 with modbus protocole. We are planning to use ST Microchips branded microchips in our project l,ke STPMC1. If you can visit www.st.com, &quot;smart energy and metering&quot; there are lots of useful data and design resources you can find.Inform us about your thoughts about this project.regardsGüçlü Ceyhan

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  • $833 USD Mar 20, 2014

    The task is to design a working Xilinx DSP system generator(sysgen) design, sysgen is a module of blocks integrated to simulink in order to automatically generate a vhdl code and bit stream to be uploaded in a FPGA board without conversion.The design should be of a 2x2 Multiple input Multiple Output system using OFDM( Orthogonal Frequency Division Multiplexing), using any encoding technique (BPSK,QPSK,QAM) with Alamouti&quot;s Tx. Technique in the transmitting side and any detection technique on the receiving side.Here are few papers that will help you understand more what it is trying to be done,

    [more]
  • $100 USD Mar 19, 2014

    Hello,I am looking for somebody who is very professional in VHDL program.I have a paper need to be implement using using Quarter II v.13 this paper and use waveform for show the result.1.Description for code 2.Write report 6 pages about the topic and result

    [more]
  • $150 USD Mar 5, 2014

    HelloI need someone to help me in writing vhdl code .. If anyone perfect with vhdl let me know

  • ₹2500 INR Feb 26, 2014

    i want a vhdl code expert to explain my project codes.

  • ₹1750 INR Feb 26, 2014

    i want a vhdl code expert to explain my project codes.

  • £35 GBP/hr Feb 25, 2014

    Implement a Serdes a full duplex communication system between two microcontrollers, with 16 datablock buffering. The Serdes implemenation will also include auto sync lock. Data will be passed in 16 byte blocks, with interface to the microcontollers being 16 bit

    [more]
  • $250 USD Feb 24, 2014

    Project could be- Develop for testing in FPGA- Redesign for ASIC- Assembler/C compiler for easier programmingfor details contact me with ur previous works

  • $200 USD Feb 7, 2014

    see the attached file for complete description

  • $440 USD Feb 4, 2014

    Design a DDR2 memory controller as per the attached PDF. The target FPGA is XC6SLX45-3CSG324C, and the DDR2 memory is MT47h64M16HR-25E. The DDR2 is configured with 4-x 32 bit ports. All the brown blocks on the schematic are Xilinx Coregen parts (DDR2 controller and FIFO memory). 4 VHDL components need to be written (green boxes). 1- FIFO-IN_CNTL This component will constantly read the FIFO and write the data in a circular buffer in the DDR2 memory. The circular buffer will be defined from address 0 to the 32-bit (DDR2-size) signal parameter. 2- FIFO-OUT_CNT This component will constantly monitor the FIFO Full pin, when it is no longer full, you will read the DDR2 memory and fill the FIFO (always keeping the FIFO full). The DDR2 will be a circular buffer defined from 0 - the size parameter 3- The thrid component is the wishbone controller. This is a slow speed interface, and the component will be used twice (ports 3 + 4). The Wishobone interface should support 32bit, 16bit and 8bit reads/writes 4- The forth component is a simple timing block which takes the 50MHz input clock and generates what ever clocks are needed for the design. Finally, the top.vhd file is required to link all coregen and vhdl components together, along with a constraints file.

    [more]
  • $244 USD Jan 30, 2014

    This is a school assignment that requires us to design a simple 5-stage pipeline CPU. It should be able to detect data hazard and insert bubbles into the pipeline accordingly.This is the description of the assignment:https://drive.google.com/file/d/0B1FhajfkRhNsdXFRemdNejhVMzQ/edit?usp=sharing

    [more]
  • $1000 USD Jan 25, 2014

    I need if u have experience with building a fpga miner that can make 20.000 khash.the alogormy is : SCRYPTLet me know if u understand this.Kind regards,T Tran

  • $1000 USD Jan 17, 2014

    Hi,We will have our first FPGA litecoin miner prototype ready within the next 2 weeks, but we still need someone to prgramm the FPGA´s. We use Xlinx FPGA, and as I have seen on your portfolio, you have some experience with them. Looking forward to work with you.

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    ahmedmohamed85 does not have any open projects.
    ahmedmohamed85 does not have any work in progress.
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Portfolio

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Résumé

Experience

Work experiance

Jul 2007 - Present (6 years)

A & A

More than 5 years working in digital system design and Developing a complete VHDL Projects for Converting old digital systems based on TTL technology into small compact unites based on FPGA's.

Education

Bachelor of Electronics Engineering

2002-2007

Certifications

Certificate of merit

Thales Raytheon Systems

This Certificate has been awarded to me for the VHDL solutions that i had provided during the work in this project.

Publications

FPGA IMPLEMENTATION OF FLOATING-POINT COMPLEX MATRIX INVERSION BASED ON GAUSS-JORDAN ELIMINATION

Sherif Moussa, Ahmed M.Abdel Razik,Adel Omar Dahmane, and Habib Hamam

This work presents the architecture of an optimized complex matrix inversion using GAUSS-JORDAN elimination (GJ-elimination) on FPGA with single precision<br />floating-point representation to be used in MIMO-OFDM receiver. This module consists of single precision floating point arithmetic components and control unit which perform the GJ-elimination algorithm. The proposed architecture<br />performs the GJ-elimination for complex matrix element by element. Only critical arithmetic operations are calculated to<br />get