Altera de1 jobs
We have a 4 output DVB-ASI Streamer PCIe card. For the PCIe function we use a PLX device which is now obsolete. We wish to use an Altera device for the PCIe function & increase the outputs to 8 independent outputs + 8 copies in the new version. Full development is ideal. But are also able to carry out some of the tasks.
We have a 4 output DVB-ASI Streamer PCIe card. For the PCIe function we use a PLX device which is now obsolete. We wish to use an Altera device for the PCIe function & increase the outputs to 8 independent outputs + 8 copies in the new version. Full development is ideal. But are also able to carry out some of the tasks.
I’m starting my final-year project by taking the MathWorks example “Designing a Guidance System in MATLAB and Simulink” and turning it into a hardware-in-the-loop demonstration that off-loads the control algorithms onto an FPGA—ideally the Altera DE2-115 I already have on my desk. Right now I’m at the initial setup stage, so everything is still in pure Simulink. Your role is to guide me through the FPGA-in-the-Loop (FIL) workflow, get the controller blocks synthesised, and prove they behave identically once they’re running on silicon. Sensor integration and data logging can wait; the immediate focus is control-algorithm work and, in particular, thorough algorithm testing after it lands on the chip. Deliverables • Partitioned Simulink mode...
...remotely using our servers and follow a structured workflow that includes version control, automated analysis, and verification. The ideal candidate is proactive, detail-oriented, and comfortable working on real FPGA design tasks, from module development to system-level integration. Responsibilities Design, implement, and verify VHDL modules for FPGA-based systems. Work with Xilinx (Zynq) and Intel (Altera) FPGA platforms. Integrate and debug high-speed serial protocols such as Aurora, SDI, HDMI, 10 GbE, and other Gbps transceiver-based links. Support signal processing and video processing implementations on FPGA. Contribute to testbench development, regression testing, and documentation. Use Tcl and Python scripting for automation, design flow customization, and tool interacti...
I need an FPGA expert to read and display TX/RX values from 12 SFP modules via I2C on an Altera Cyclone FPGA. The output should be shown on an LCD screen. Key Requirements: - Use I2C to communicate with SFP modules. - Read TX/RX values and process them. - Display values on an LCD screen. Ideal Skills: - Proficiency in Altera Cyclone FPGA programming. - Strong knowledge of I2C protocol. - Experience with LCD interfacing and display logic. Please ensure your bid includes relevant past experience with similar projects.
I am seeking a freelancer to implement a traffic signal controller using the Altera DE2-115 board. The project is intended for educational demonstration purposes, so clear and effective design is crucial. Key Requirements: - Use of Verilog to program the board. - Implementation of a fixed-time sequence traffic signal pattern. - Inclusion of pedestrian crossing signals, which should be activated via the board's key button. - Utilization of the board's LCD screen to display the current signal state. Ideal Skills: - Proficiency in Verilog programming. - Experience with the Altera DE2-115 board. - Understanding of traffic signal patterns and controllers. - Ability to design for educational purposes.
Looking for someone that is an expert in Altera cyclone to help me figure out the issue am having with my blaster connection. Circuit is good and all voltages are in the right place but am not able to connect to Cyclone 3 chip with Quartus
...skilled PCB designer with experience in multi-layer layouts, specifically for industrial equipment. Key Requirements: - layouta multi-layer PCB incorporating various components including an FPGA, ADC, power regulator, TI DDC114, and DAC. Design has already been done, layout as well, but layout is not done well and must be redone. The existing design will be provided as Altium set of files. Since Altera can export to other formats it would be okay to use other tools as well as long as Altium can re-import the format. - Ensure that the design is robust and suitable for industrial use. Ideal Skills: - Expertise in multi-layer PCB design - Experience with industrial equipment - Proficient in using PCB design software - Knowledgeable in integrating components like FPGA, ADC, powe...
Looking for an Electronic engineer that understands Digital systems that can evaluate my circuit, simulate and see any issues that could be happening on it. MUST HAVE EXPERIENCE WITH ALTERA CYCLONE FAMILY CHIPS MUST HAVE EXPERIENCE USING ALTIUM Needs someone to start immediately
...phase. Assist in performance testing and optimization of FPGA designs. Requirements: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 3-5 years of experience in FPGA design and development. Proficiency in hardware description languages (HDLs), such as Verilog or VHDL. Experience with FPGA design tools and simulators, such as Xilinx or Altera Quartus. Understanding of digital signal processing (DSP) concepts and architectures. Knowledge of FPGA-based system architectures, including memory interfaces and communication protocols. Excellent problem-solving skills with an attention to detail. Strong communication skills for collaboration with other team members. Ability to work independently and as part of a tea...
I'm looking for an individual with expertise in Altium Designer. This project involves replacing an obsolete Xilinx FPGA with an Altera part. The initial project has been done in Altium Designer. ECAD would need to be done in Altium 19.
...freelancer with expertise in FPGA coding to bring a custom logic design project to life in Noida (Delhi/NCR). **Project Objectives:** - Development and implementation of custom logic designs using FPGA. - Ensuring designs are efficient, reliable, and meet project requirements. **Skills and Experience:** - Strong background in FPGA programming and design, with specific experience in either Xilinx, Altera, or Lattice platforms preferred. - Proven ability to develop and optimize custom logic designs. - Excellent problem-solving skills and creativity in designing unique solutions. - Ability to work independently and deliver project milestones on time. **Application Requirements:** - convert LVDS signals to MIPI CSI2. - preferably using Lattice crosslink. This project offers an ex...
I'm seeking a talented individual with a strong background in VHDL and FPGA design, specifically with Altera products, who can successfully implement communication interfaces within my project. The ideal candidate will possess a deep understanding of UART protocol and be capable of integrating it with other interfaces. Requirements: - Proficiency in VHDL programming for FPGA - Experience with Altera FPGA design tools - Successful implementation of UART interfaces - Knowledge in LAN and USB communication The scope of the project includes: - Implementing a low-speed UART interface (up to 115200 bps) - Integrating UART with LAN and USB interfaces on the FPGA The right freelancer will have a strong portfolio demonstrating their expertise in FPGA interface design and commu...
I am looking to hire a freelancer to design an FPGA function generator using a Altera MAX 10 FPGA, 10M08SAE144C8G that produces a frequency of 10 MHz and above. The desired waveforms are sine, square, and triangle. This function generator should also have a single channel. If you think you have the skills to help me with this project, feel free to bid on it. Thank you!
My project is about FPGA programming for control systems. I'm using the Altera Cyclone V board and the preferred programming language is Verilog. This project requires someone with experience in FPGA programming and the design of embedded systems. The programmer should be able to develop design flows for FPGA devices, debug them and modify existing designs for better performance. The knowledge of hardware description languages such as VHDL and Verilog is crucial, as they will be used for implementation and testing of the designs. Additionally, some knowledge of microcontrollers and communication protocols will be required. The right person for this job should have strong problem-solving skills, excellent coding and debugging capabilities, and a deep understanding of hardware in...
Project Title: Altera DE0 Board Programming Assistance Description: I am seeking a freelancer who can provide programming assistance for my Altera DE0 board project. I require expertise in VHDL programming language and the ability to modify existing code as well as start from scratch. Skills and Experience: The ideal candidate for this project should have: - Proficiency in VHDL programming language - Experience with Altera DE0 board - Strong troubleshooting and debugging skills - Knowledge of hardware design consultation Specific requirements: - Provide programming assistance for the Altera DE0 board - Modify existing code and develop new code from scratch - Troubleshoot and debug any issues that arise during the programming process - Provide hardware design ...
Hello,I am looking for devs who has experience and knowledge in FPGA to interface RF AFE chip from analogue device(exact part number via chat) Desired FPGA- xilinx Zynq/ equivalent series, Cyclone/equivalent from altera. The FPGA will be interfaced with the AFE and will act as an DSP. Apart from the AFE the FPGA is expected t be interfaced with: 1) Display module 2) Keypad 3) Memory 4) Microphone 5) ESP32C3 and GNSS module. Additional MCU/processor can be added to reduce the burden on FPGA. It can be decided after discussing. The FPGA will perform the DSP task and will be used to transmit RF waveforms. It will be used to perform frequency hopping and encryption (AES-256/SHA) task for the waveform. More detailed information via chat. Eligibility: The freelancer must have...
I am an EE engineer. I have lots of experience designi...Assembly language and C/C++ (both procedural and OOP). *for STM and nrf controllers Mbed OS could be one of the choices for programming the MCU. I have done lots of projects in the field of wireless communication and IoT using different wireless communication protocols like BLE, RF, WiFi (Cloud), etc. In the field of bit streaming, high-speed processing and ML, I am able to program both Xilinx and Altera in VHDL or C/C++ for Microblaze or NIOS II processors. For manufacturing purposes, I can provide component selection and BOM which suits your needs for a durable, efficient, and effective design. ABOUT YOUR PROJECT, I have done lots of similar projects before and can handle your project easily. We may discuss it more over cha...
...developing co-design projects. There are many possible solutions to the design problems depending on the way in which you choose to partition each problem. HW/SW Specs: The target embedded systems platform can be either the AlteraDE0 FPGA platform or the PSOC. Both devices/boards provide the opportunity to implement low-level, interrupt driven, device drivers along with the custom hardware. Altera DE0 Board: This board has a Cyclone III FPGA fitted. This supports a ’soft-core’ processor integrated with custom hardware. Using the Nios2 softcore CPU as a base you will implement a system to control a robot arm. There is the potential to use a small embedded O/S, FreeRTOS, uCLinux, or to write your own scheduler for this solution. PSoC: PSoC is industry&rsqu...
Brief – Postcode Data Sorted – 210323The job is to filter a list in Excel of all the records which have postcodes starting with: 1) B1 – B99 2) LE1 – LE67 3) CV1 – CV47 4) DE1 – DE99 5) NG1 – NG99
Hi, can you help me out to code Verilog coding for the sound detection sensor for turning on the LED on DE1 SoC Cyclone V board?
I have a board i need to fix for an equipment in my store. Looking for an FPGA expert that can debug the program files i got from the manufacturer. I was told this should be simple for someone that knows what they are doing.
...filters (like hq2x) 4. output from scaler is passed through optional scaline generator, where scanline parameters are passed as input wires : scanline color, scanline thickness, scanline interval 5. output is overlayed by the bitmap OSD with the same resolution as output format Requirements : aside from the DDR memory interface, or PLL no vendor or encrypted IP blocks can be used, for example no Altera/Intel video pipeline. Everything must be in written verilog source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed m...
Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.
Implement the circuit design in the FPGA, and read input /write output to the file. Including timing analysis, power consumption and pin planner etc... Using Quartus prime
To create user-level Linux programs that produce audio output on the DE1-SoC board. The task is to implement a digital piano that can play musical chords through the audio port of the board.I just want the code till part3 in the pdf which is present below. skeleton code for those and header files, address files also present in the design files
Read the pdf. the 7 segment LEDS can be used to show the frequency. The main job is to build a NCO that creates frequency between 10 hz to 10 Mhz and then read it on a frequency meter with 1 Mhz clock and display the value on 4 digit 7 segement LED.
I m looking for a fpga design for an BPSK demodulator, the fpga ill be using is altera, i ll also require an simulink file illustrating the functionality of the demodulator, i provide the input file for the demodulator.
Write VHDL code and testbench for the given question and simulate them using Quartus and Modelsim Altera
Design a fully digital, hardware-based direction discrimination and counting system for use with quadrature encoder-based rotatory incremental encoders.
This is a final year project. We are struck with simulation. Need to debug our program, or else develop the project from scratch. I am attaching the code that we have wrote for your reference. We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2. There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'. From what I understood, the main issue is the interconnection between all the modules.
Hello. I have a sales system (ERP) that has an open API. I need and a BOT/System that whenever a sale happens, the bot sends a message to my client via whatsapp. System API is very complete. The API notifies you when there is a sale, the API has all the customer's data such as Phone number, Name, Address, emai...thank you message, with order information (information is available in the API) Bot need use my own mobile number... Invoice API: Order API: Callback Status order: ( portuguese, translate to your language )
Write a program using QUARTUS ALTERA to work on De1-SoC FPGA BOARD. .................. The LED Brightening Control with an Absolute Encoder The circuit to be designed must provide control of the brightness of a single or multiple LED ‘s using values from an Absolute Contacting Encoder (128 positions). In addition, the circuit must display a decimal value of the LED intensity (0-127) by using three seven-segment displays. The circuit contains four logic blocks and 3 external components (Figure 1). The logic circuits are: • Code Conversion Table • Binary to BCD 3 digits (Decimal Values) • LED Brightening Control (PWM) • Seven Segments Decoder
Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart and Mnemonic document state diagram.
In this project I want to see how the ADC works in FPGA kit .. with any sensor LED or temp. The board is ALTERA Cyclone IV EP4CE6e22cb
Looking for a tutor on Quartus Altera/Intel MAX10 FPGA device. Knowledge of QSYS, Platform designer, Eclipse, HDL/VHDL. Embedded system control design using FPGA. Closed loop control ADC sampling, PI controller , PWM generation in HDL/VHDL.
Looking for website content for Power electronics converter for battery chargers for EV market. Magnetics design , Embedded software FPGA. Altera/Intel VHDL.
Hello, In my project I need to store data on my FPGA Altera EVMs. The data must be stored on a non-volatile device (power done can occur at all time). To do that, I need to implement an interface to the on board uSD card. Here are some specification: 1. SD Card: Class 10, 2GB. 2. Min write speed: 200Byte every 1ms (effective) ~1.6Mbps. 3. Read speed: 10Mbps (Flash all mode) 4. All VHDL (NiosII- only when guaranteed performance). 5. Full Duplex- Optional. 6. Target: DE10-Nano and DE2-115. 7. Delete all data function: optional. Thanks, Idan
VHDL , QUARTUS , MODELSIM ALTERA, QUESTASIM, UP DOWN COUNTER , COUNT ZERO COUNTER, CLOCK GENERATOR, RGB CONTROLLER. STATE MACHINE ...
The AD 9254 is to be interfaced with TERASIC DE4(Altera startix IV) in DSP builder platform
Hi I need an expert in these two software Altera Quartus II Computer Aided Design Software and Modelsim-Altera Simulation Software. inbox me for more details.
1. Encode key presses on a standard 16-key 2. give a stable 4-bit binary output 3. Have output to indicate when a key is being pressed.
to design and implement a game clock on the DE1-SoC development board, using any of its on-board resources (buttons, switches, seven segment displays etc.). The game clock should have two modes of operation to allow the following variations: • The first mode of operation should give each player a fixed amount of time for the whole game. There should be a suitable indication if either player runs out of time. • The second mode of operation should be a game clock variation of your choice. You should produce a report (maximum 1500 words, excluding appendices), in pdf format, that gives a comprehensive account of the design process including the hardware setup, VHDL code testing and evaluation. It should also include: • Instructions for the user. • The full set of...
You are required to design and implement a game clock on the DE1-SoC development board, using any of its on-board resources (buttons, switches, seven segment displays etc.). The game clock should have two modes of operation to allow the following variations: • The first mode of operation should give each player a fixed amount of time for the whole game. There should be a suitable indication if either player runs out of time. • The second mode of operation should be a game clock variation of your choice. You are free to decide the user interface, but the following should be kept in mind: • A minimum of user interface hardware (such as buttons) should be used. • The user interface should be as easy and intuitive as possible. • The VHDL design should use the...
Dissolve DDR3, FlyBy topology, 2 Altera SoC chips. 8 layers (S-P-P-S-S-P-P-S), 3 (4, 5, 8 layers) available for DDR wiring. Changing the placement of components is acceptable if critical. Alignment rules and signal classes are defined. Deadline until 28.02. It is possible to expand the order to a complete layout of the board with an increase in cost and extension of terms.
We are looking for a developer who has experiance in Embedded Application Programming. Typical Operating Systems Embedded Linux Android FreeRTOS μC/OS ARM, MIPS, Motorola, ST, TI, Microchip... Arduino Xilinx MicroBlaze (Softcore Processor) Xilinx and Altera FPGA (see Electronics Overview) Identifying and removing bottlenecks with performance analysis and tracing tools. Using low-level languages such as C or assembler for greater control over resource usage. Developing unit tests to quickly verify software modules on higher performance machines. Tuning code for low memory usage and looking for memory leaks using tools such as Valgrind. Preventing memory leakage by using static allocation if necessary (for example in a safety critical application). can develop user interfaces...
I need guidance with Altera Quartus and introductory Logic Design/Electrical Engineering work.
I need a project made with the software Quartus. My board is using an Altera chip, model: EP4CE6E22C8N. I need a 8 bit calculator, that uses a matrix 4x4 keyboard and display the results in the 7 seegments display that my board has. Board model: RZ-easyfpga a2.2 I attached on the job the pin diagram of my board.
