Asic fpga vhdl rtl verilog jobs

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    10,247 asic fpga vhdl rtl verilog jobs found, pricing in USD

    VHDL and FPGA system using vivado program.

    $655 (Avg Bid)
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    7 bids

    I need you to develop some VHDL software for me. Must have good VHDL background. Message me for more details. Thank You.

    $44 (Avg Bid)
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    5 bids

    I need a vhdl task done along with report

    $30 (Avg Bid)
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    Looking for a Vivado Studio Specialist to evaluate code. On a Zturn board ( Xilinx Soc 7000 Series.) Skills required: AXI RTL Vhdl Vivado Studio

    $124 (Avg Bid)
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    2 bids

    You have to complete coding and report writing

    $67 (Avg Bid)
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    5 bids

    I want the verilog UART code along with pin assignment, synthesis and waveform outputs using Quartus II tool on ALTERA DE2 Board.

    $48 (Avg Bid)
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    3 bids

    An existing DDR3 controller shall be migrated to the following platforms / DRAMs: - 3 times as existing, but different pinout (in total 4 controllers need to co-exist on 1 FPGA) - 2 times to a 32 bit wide 128Ms deep, dual die (2x16bit) configuration - 1 time to an 8 bit wide 128Ms deep, single die configuration for the first configuration, the write & read speed shall be at least 200MHz, 3...

    $602 (Avg Bid)
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    احتاج احد فنان في الوردبريس و يقدر يخليه RTL بطريقه غير البلغ ان ..

    $25 (Avg Bid)
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    13 bids

    GMT is a financial services company. We are looking for a css specialist for some css work on a Vue Js App. The project is to fix an element which has a line and several dots on it with text that needs to be positioned correctly in 2 different language alignments (rtl or ltr) and on different devices also in 2 alignments.

    $159 (Avg Bid)
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    9 bids

    I need a block to select some outputs based on the input and previous values of the input in VHDL

    $30 (Avg Bid)
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    Project goal is a detailed pin planning and block diagram for a JESD204B data converter application. The following components will be disclosed to applicants: - ADC - FPGA - PLL The interface will work at speeds up to 12.5Gb/s. ADC sample rate will be up to 1Gs/s The deliverables for this project are: - Spreadsheet with pin assignments from FPGA to ADC - Spreadsheet with pin assignments from FP...

    $174 (Avg Bid)
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    3 bids

    Multi vendors Vendors by Geolocation RTL support with arabic language Barcode scanner Order list Order for later SMS notification and OTP verification Push notification Multi address Expiry date notification for products Reward points Discount Auto coupon system

    $2900 (Avg Bid)
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    136 bids

    Product suggestions for a high volume/high demand (tens of thousands to hundreds of thousands) FPGA based consumer product using A3P series FPGA from Microsemi. Product must be easy-intermediate difficulty to design Verilog/VHDL and final manufacturing cost in $30-$50 [login to view URL] as little other electronic components as possible. There is a possibility of design collaboration for winning e...

    $110 (Avg Bid)
    Guaranteed
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    8 entries

    Design a 4 bit up-down multi-function counter using NEXYS 4 DDR (Artix-7 FPGA) board. The counter should display the count every 10 seconds. The counter will have a reset switch (SW0) or button to initialize the sequence to (0000) when it is 1, direction switch (SW1) to select the counting direction and a counting mode switches (SW2and SW3) to select the counting mode. The output should be display...

    $155 (Avg Bid)
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    1 bids

    Interesting project for 3D-Metrology

    $45 / hr (Avg Bid)
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    2 bids

    Need good FPGA programmer for Ethereum Crypto Mining Need to set up mining rig like this [login to view URL] Tell me in detail your experience in crypto mining and tell me also in detail what specific tasks that you will perform to complete this project

    $18 / hr (Avg Bid)
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    9 bids

    Need good FPGA programmer for Ethereum Crypto Mining Need to set up mining rig like this [login to view URL] Tell me in detail your experience in crypto mining and tell me what you can do to set this miner up for me

    $153 (Avg Bid)
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    4 bids

    Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relation with the perfect electrical engineering freelancer. I need to hire 3 freelancers for 3 copies of the task. Thanks.

    $126 (Avg Bid)
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    I have a small company and need PCB design services from time to time, when my in-house designer is overloaded. This job is pretty straight-forward.

    $995 (Avg Bid)
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    14 bids

    I need a random number generator which will work on a fpga board and the code should be written in xilinx, should be a vhdl code

    $27 (Avg Bid)
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    I need a coder who can code on fpga board and create a ultra low latency financial execution platform for algorithm trading equity stock market.

    $31520 (Avg Bid)
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    9 bids

    I need a developer who has worked on fpga board or worked on ultra low latency financial domain..we have to build in-house stockt market trading execution platform..

    $10699 (Avg Bid)
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    I have the Deo Nano Soc and I want to read data using DMA. I need to read at a rate of about 2MB/s. I have used VHDL for a while and if you could provide some protocol/instructions at the top level, I could do the rest.

    $127 (Avg Bid)
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    6 bids

    VHDL Project with registers for small business.

    $90 (Avg Bid)
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    Starting a small business programming registers, buttons, and switches on my FPGA board in VHDL. Looking to hire a programmer that knows basic/simple vhdl coding skills and can complete the startup within a few days preferably.

    $62 (Avg Bid)
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    A project to implement a calculator(ALU) in Verilog code using Quartus program I need a detailed report with state diagram and finite state machine I need one who can access my computer to teach me how to do the settings of the program also the Verilog code will be implemented on ALTERA board(DE2-115) also I need instructions of how I can run on the board (its due Saturday sharp)

    $56 (Avg Bid)
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    I need help creating wordpress WP theme design support RTL / LRT - same as this theme ( [login to view URL] ) as a main page - and inside page will be same as this ( [login to view URL] ) no time i need the owrk to be done within 24 hours .

    $169 (Avg Bid)
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    Project is to create C/C++ software to program Altera FPGA (MAX10) configuration memory from an embedded ARM processor using Altera JAM tools. The target device is MAX10 16M, and embedded CPU is Kinetis. The software must read a JAM file and program the FPGA configuration memory using the JTAG interface, which is bit-banged from the MCU pins. Deliverable is a C/C++ program for the JAM programming...

    $2480 (Avg Bid)
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    Microprocessor design project using system verilog in Modelsim and physical validation on Quartus Prime. I have started writing code for some of the blocks. The Register file, ALU and Instruction memory are nearly complete. Assistance needed in writing the remainder of the blocks: the instruction register, the micro controller unit, the W register, the program counter and anything else needed to w...

    $139 (Avg Bid)
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    Hi I'm looking for a good vhdl programmer to help me with a code. I'm supposed to bring in a simple logo, then i,m supposed to be able to display the logo on the center of a screen(using a vga connection) and my name on the bottom left corner while being able to flip the logo with a button on my fpga board the deadline is thursday. thank you. I have the initial codes. I'll provide m...

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    Implement RTL version of a websites account area

    $446 (Avg Bid)
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    We are working on an FPGA based doppler flowmeter with a custom PCB. At the moment, we are in the process of modeling algorithms using raw data recording in Matlab. This freelancer will be tasked with coordinating with the DSP engineer to design and implement changes from the Matlab models into our custom PCB, which Cyclone IV based. There is an existing version of both the recording firmware and ...

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    We need to move a wordpress site to a full Laravel codebase. The wordpress is multilingual and we need to migrate the "translation capabilities" to the new laravel backend, because we need a team of translators to keep adding new languages from the backend, including RTL languages, Chinese, etc. This is the wordpress web we need to move to laravel: [login to view URL] We need to maint...

    $1491 (Avg Bid)
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    87 bids

    we looking for Build wordpress site blog need bearticals a lot by category. basic home page about us page and contact us page articals category will be with sub category the website will be in hebrow only. so support RTL fully. made fit to SEO. dayes to complate - 2 days.

    $119 (Avg Bid)
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    I have a digital input measurement signal, 0 ~ 1.1V level. Each pulse is an event, that has a level HIGH width from 5ns to 10ns, and the minimum time between every 2 pulses' rising edges is 20ns. I need a system to histogram the time between all adjacent pulses' rising edges, that each bin of the histogram is 1ns wide. For example, starting from t=0, if the input signal has rising edge...

    $1100 (Avg Bid)
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    Grocery mobile app Build on opencart Multi vendors Vendors by Geolocation RTL support with arabic language Barcode scanner Order list Order for later SMS notification Push notification Multi address Expiry date notification for products

    $2566 (Avg Bid)
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    I need you to develop some software for me. I would like this software to be developed for Windows using Verilog/VHDL.

    $10 - $30
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    Create verilog code for an Alarm clock with testbenches. Alarm clock will display on 7 segment display. More information available upon request. Simple Project

    $155 (Avg Bid)
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    1 bids

    I need to design a multi layer FPGA PCB in altium.

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    Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read enable from data bus (active low) a chip ...

    $199 (Avg Bid)
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    Make Native apps with Arabic : Apps are already built in English, just need to make them in arabic. Translations will be provided.

    $10 / hr (Avg Bid)
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    21 bids

    I am enclosing description in the files.

    $38 / hr (Avg Bid)
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    Hi, Need to add RTL support to this app in codecanyon : [login to view URL] and want to add some details to it Regards, Imad

    $182 (Avg Bid)
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    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    $29 (Avg Bid)
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    Document with full requirements will be shared once discussed with person up for the job. Verilog code in top down design for a 4-bit ALU. A test bench will be needed to test design and needs to be able to program DE0-CV FPGA board to implement the full design.

    $98 (Avg Bid)
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    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    $155 (Avg Bid)
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    2 bids

    we have a design and we want to implement it into [login to view URL] with full needed customization with RTL

    $154 (Avg Bid)
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    Verilog needed to be used Please if you can in between the main block of codes if you can explain the function of that certain code, such as lowering the intern clock to 10Hz, or what not. Thanks

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