Atlys xilinx jobs

Filter

My recent searches
Filter by:
Budget
to
to
to
Skills
Languages
    Job State
    527 atlys xilinx jobs found, pricing in USD

    inbox me for more details thanks please reply soon i am waiting ...............................................................................................................................................................................................................

    $114 (Avg Bid)
    $114 Avg Bid
    26 bids
    xilinx project 4 days left

    inbox me for more details thanks please reply soon i am waiting ...............................................................................................................................................................................................................

    $79 (Avg Bid)
    $79 Avg Bid
    1 bids

    Given the Open Cores from the open cores project I want a simple module that is able to do the following on a Xilinx ZedBoard: 1. Given 256 bit BITKEY, scramble the input with a hard coded IDKEY in the FPGA and provide a AESKEY 2. The same response needs to be piped to an AES256 module from OPEN CORES in order to encrypt/decrypt a stream of data

    $154 (Avg Bid)
    $154 Avg Bid
    6 bids

    This is extremely simple but urgent!!! You are asked to provide a simple Xilinx Spartan 6 FPGA program that reads data from multiple I2S input ports and then aggregate them into a single data stream and output through uart or I2s or USB.

    $1102 (Avg Bid)
    $1102 Avg Bid
    13 bids

    UDP data filtering using Xilinx Zynq 7000 family Socs (10 Gb SFP+ port)

    $1277 (Avg Bid)
    $1277 Avg Bid
    8 bids

    ...accordingly with the board. I can provide the ucf connection file that shows the connections of the Marvell chip to the fpga. You must work exclusively in VHDL and preferably in Xilinx ISE Suite (however that is up to you as long as the code works). I need this done by Friday 7th July. This is a quick task for someone who knows their work. You will have

    $136 (Avg Bid)
    $136 Avg Bid
    6 bids

    сделан не большой алгоритм в Simulink для Xilinx ultrascale+ с применением Xilinx system generator блоков Надо из симулинка вывести HDL код и закинуть его в Vivado для оценки ресурсов

    $2135 (Avg Bid)
    $2135 Avg Bid
    5 bids
    $110 Avg Bid
    12 bids

    Implement algorithms in Xilinx FPGA writing Verilog / VHDL code to generate optimize RTL and create software to test and characterize the algorithms.

    $2493 (Avg Bid)
    $2493 Avg Bid
    12 bids

    I want to implement a 2-D FFT on an Xilinx FPGA board Artix 7 chip, it will be used for Radar signal processing.

    $208 (Avg Bid)
    $208 Avg Bid
    18 bids

    I need someone to make some change to some VHDL code.

    $19 (Avg Bid)
    $19 Avg Bid
    12 bids

    I need someone to make some changes to some VHDL code.

    $23 - $193
    Local
    $23 - $193
    0 bids

    I need someone to make some changes to some VHDL code and test on xilinx.

    $8 - $23
    $8 - $23
    0 bids

    hey bro,the project is something similar to what i have attached in the file you have to design a circuit and execute in xilinx software

    $13 (Avg Bid)
    $13 Avg Bid
    1 bids

    ...VerySimpleCPU with everything in the .asm file (program and input data). 6) You may then simulate your design (VerySimpleCPU.v), tb.v, and blram.v in VerilogTB folder using Xilinx ISIM (part of Xilinx ISE design suite). 7) If your design is working, meaning if you see the "after =" values in the memory locations marked in [url removed, login to view], then your design is...

    $55 (Avg Bid)
    $55 Avg Bid
    8 bids

    I need a VHDL coder for xilinx. I have a lab work to be done.

    $82 (Avg Bid)
    $82 Avg Bid
    12 bids

    I need someone that is an expert in VHDL coding and Xilinx. For 2 projects More details will be provided upon request.

    $244 (Avg Bid)
    $244 Avg Bid
    16 bids

    I need Verilog code for fused multiply add unit for single precision floating point unit. The code needs to run on a Spartan 6 FPGA. I will run it here on Xilinx ISE.

    $434 (Avg Bid)
    $434 Avg Bid
    7 bids

    ...acceptable and clear document. 2. At the end, the final source code should run on the Parallella board with the least efforts and you should show how to run this code in Xilinx Vivado tool set (by PDF or short video). Also the resource utilization of the FPGA (Number of Slice Register, Number of fully used LUT flip-flops pairs, Maximum operating Frequency

    $203 (Avg Bid)
    $203 Avg Bid
    6 bids

    ...interface code, need to program Xilinx FPGA spartan 6E where it should be able to transmit and recieve data via putty. Then build calculator on FPGA so that for example if send 4 +5 to FPGA via putty, the FPGA should transmit 9 to putty. So far, I have a test bench to analyse the simulation produces on sim, xilinx software. The test bench shows that

    $56 (Avg Bid)
    $56 Avg Bid
    8 bids