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2,389 convert verilog vhdl jobs found, pricing in USD

I have an assignment that my lecturer asked me to do and the deadline is 28/7/2017. I need to show him the simulation that the program is running and may be few basic question. I want someone to do the assignment and show me how I have to show to my teacher that the program is running (simulation). I have attached a file where there is 3 question. But I only need to solve question 2. That is "...

$28 (Avg Bid)
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2 bids

I would like to hire a developer who can work exceptionally well in VHDL and is good in algorithms

$375 (Avg Bid)
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18 bids
Design block in VHDL 5 days left
VERIFIED

Mirror unit receives data stream via Avalon ST interface which is buffered and processed if necessary. Each steam starts with Control packet which contains description about the image like interlacing, width and height or definition of the data received (Altera's VIP has it's own protocol, it is assumed that you familiar with it). Please read attached document for more detailed descr...

$462 (Avg Bid)
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3 bids

I need you to develop some software for me. I would like this software to be developed . Alu/register file in vhdl

$138 (Avg Bid)
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11 bids

Digital down converter , Digital Up converter VHDL & Matlab . DDC: 1- Fsample : 16 bit x 400 MSPS Max. 2- Bandwidth : programmable from 100Khz to 20Mhz. 3- IF Tuner : programmable from DC to 100Mhz , resolution [url removed, login to view] . 4- DDC decimation Range : 8 to 4096 . 5- CFIR : programmable 20 taps( 18 bit coefficient ) . 6-

$536 (Avg Bid)
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12 bids

Estimation of Power of an FPGA by using complex VHDL codes is the main task of the project, I need help with the VHDL .

$584 (Avg Bid)
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16 bids

(vinodluhar's) 10G sfp+ port will be read , using xilinx's free IPs , udp data will be filtered out, based on udp data content, and will be passed to other ethernet port, memory and ACP port of Zynq, using AXI interface with test bench for simulation.

$1194 (Avg Bid)
$1194 Avg Bid
9 bids

(vinodluhar's) 10G sfp+ port will be read , using xilinx's free IPs , udp data will be filtered out, based on udp data content, and will be passed to other ethernet port, memory and ACP port of Zynq, using AXI interface with test bench for simulation.

$1250 (Avg Bid)
$1250 Avg Bid
1 bids

I am looking for developer for digital signal Processing , I need VHDL code for : 1- Digital Up converter . 2- Digital Down Converter . 3- SSB , LSB , USB , ISB Modulation / demodulation . 4- AME Modulation/ demodulation 5- FM Modulation/ demodulation . 6- FSK Modulation/ demodulation 7- GMSK Modulation/ demodulation 8- QAM Modulation/ demodulation

$2568 (Avg Bid)
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13 bids

I need help in a verilog question. I am a beginner in verilog so need some help.

$19 (Avg Bid)
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16 bids

I need a small verilog code as soon as possible.

$271 (Avg Bid)
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28 bids

Training using Verilog Altera-Quartus

$55 (Avg Bid)
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1 bids

Training using skype and screen sharing.

$120 (Avg Bid)
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3 bids

I need a small verilog code as soon as possible.

$222 (Avg Bid)
$222 Avg Bid
21 bids
Asic Design / FPGA Ended
VERIFIED

I need someone expert in ASIC design to design digital clock with VERILOG CODE by Quartus software Contact me for more details

$140 (Avg Bid)
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16 bids

design digital clock with alarm with Verilog code / FPGA

$187 (Avg Bid)
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22 bids

sequence ending in 1110010101 design both mealy and moore machine and than test and compare their function using MAX PLUS II package on Quartus II

$50 / hr (Avg Bid)
$50 / hr Avg Bid
1 bids

Hello, I need the implementation and simulation of...I need the implementation and simulation of the FFT (Fast Fourier transformer) of the following points: 8 points, 16 points, 32,64, 128, 512 points, 1024 and 2048 points, in VHDl the program must be synthesizable With xilinix ise design software The results of the consumption slices must appear...

$22 (Avg Bid)
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8 bids

required and experienced electronics system designer to draw architecture and implementation of a bridge circuit in verilog for implementation in FPGA. need the work to be done as soon as possible

$185 (Avg Bid)
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10 bids

Implementation of Image processing algorithms on FPGA/CPLD hardware using VHDL, and Verilog, MATLAB

$1864 (Avg Bid)
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6 bids