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    3,073 fpga e1 framer jobs found, pricing in USD
    FPGA unit phasor measurements 6 days left
    VERIFIED

    First task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop The second part of the project task is to populate the ADC and final amplifier stages on the PMU PCB, together with power...

    $30 - $250
    $30 - $250
    0 bids

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

    $305 (Avg Bid)
    $305 Avg Bid
    5 bids

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

    $221 (Avg Bid)
    $221 Avg Bid
    8 bids

    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    $33 / hr (Avg Bid)
    $33 / hr Avg Bid
    1 bids
    customization of an SDR 3 days left
    VERIFIED

    We are looking at scanning,capturing and decoding multiple cellular frequencies(European 2G/3G/4G(LTE) bands) with an SDR. Currently using a simple rtl-sdr for this case but seeing as it lacks the frequency range(max 1800mhz) and has very little bandwidth(2.4MHz) we would like to upgrade to a better SDR. The goal is to analyze multiple simultaneous communication channels in real time. We are loo...

    $1491 (Avg Bid)
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    6 bids
    Build a CNN 2 days left

    Hi, I need : * CNN IN FPGA using my mac unit? *Verilog *MNIST DB

    $199 (Avg Bid)
    $199 Avg Bid
    5 bids
    PCB Design 1 day left

    Use the xtal oscillator board that I designed and that works together with the FPGA to read the GPS data and then synchronise the 40 MHZ Voltage controlled Xtal oscillator to the 1 second pulse produced by the GPS. I will provide more details on chat.

    $156 (Avg Bid)
    $156 Avg Bid
    17 bids
    FPGA expert needed 20 hours left
    VERIFIED

    I am looking for an expert in FPGA, its not a simple task, only expert place bids. will share details in chat

    $20 (Avg Bid)
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    7 bids

    Need someone who has the PLDa PCIe ipcore license for Xilinx Vivado to help compile a FPGA project. I'll give you the source code. You compile and give me the bit file and compiled project.

    $206 (Avg Bid)
    $206 Avg Bid
    8 bids

    The test program used for transmited data between DDR4 of FPGA and DDR4 of PC adopted windows 10 or win7 system via PCIe 3.0 x8. A tested result shows that the speed of PCIE3.0 *8 is over 7GB/s , which is tested by xilinx Kcu1500 FPGA board. However, the speed under win7 / win10 is only about 4.5-4.9GB/s. The minimum speed threshold should be 5.5 GB/s. And it will be helpful if the speed...

    $6804 (Avg Bid)
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    6 bids

    Need basement framed. Labor only — no materials needed. Should only take a day.

    $387 (Avg Bid)
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    4 bids

    Need basement framed. Labor only — no materials needed.

    $333 (Avg Bid)
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    3 bids

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

    $109 (Avg Bid)
    $109 Avg Bid
    6 bids

    I need an "and" keyword search program, that I will describe as if it is in Excel, but it doesn't need to be an Excel program. In Excel column A, and in each cell down to a maximum of about 850,000 rows, there will be a list of words 50 to 1000 characters long. For example: A2: cat dog rabbit mouse trap... A3: table chair stool lamp ... A4: car truck motorcycle parts ... A5: comp...

    $10 (Avg Bid)
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    1 bids

    i have projects related to all of these micro-controllers: Raspberry Pi FPGA PIC microcontroller STM microcontroller so looking for experts who can assist me with these projects

    $68 (Avg Bid)
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    19 bids

    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

    $103 (Avg Bid)
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    6 bids

    I want to make this tool by updating the hardware to a new fpga board, here is source code and some documents about it. [login to view URL]:projects:smartlogic [login to view URL] [login to view URL]

    $506 (Avg Bid)
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    12 bids

    Your challenge: Deploy a working app to apple store in 10 days. By 8/17/19. If you do well, you will be given ALOT more opportunities and work. The app will have 6 pages and is very similar ot an e-commerce type of flow: 1. Email sign up 2. Ask a question 3. Show a special product (the most popular.. just 1 product) 4. Show product details. 5. Buy the product 6. Show a list of additional prod...

    $1274 (Avg Bid)
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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

    $80 (Avg Bid)
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    9 bids

    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

    $102 (Avg Bid)
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    16 bids

    my project is about lipstick made from natural organic materials. High Quality My website in Vietnamese, you can make it with english than i give you the translation for vietnamese version I need the website easy to SEO with all tag / onpage SEO. + Chat and call button + Link to facebook pages, likes and share button + Faecbook pixels for facebook ads intergrated to action of users + Google ana...

    $411 (Avg Bid)
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    78 bids

    PANEL = Artix-7 100t - ERROR: [Labtools 27-2269] Hi, I am facing ERROR: [Labtools 27-2269] after issueing the open_hw_target command. Vivado 2019.1 Windows 10 Connected through micro USB for serial communication. MODE = JTAG Any suggestion as to how can i detect the devide to burn my bitstream for execution? Thanks!!

    $77 (Avg Bid)
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    2 bids

    Map page will be full map with 2 layer: Origin layer (from OSM) and KML layer KML layer will be provide as in attachment User interact with map will be similar to wikimapia in which user hover over a place it will light up (see attached image) when click to a place it will show custom content with link to forum custom content is similar like this http://wikimapia.org/#lang=vi&lat=20.944607&...

    $193 (Avg Bid)
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    19 bids

    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

    $222 (Avg Bid)
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    10 bids

    I have a map with coordinates (attached) I need a program that allows me to easily plot the location of accidents on this map. if i have a list of accidents, (say E1, A4, J7 etc) I need to be able to enter those coordinates and see them plotted on an online version of this map - (should be shows as a Red Dot or something that is small but visible) This needs to be highly interactive User Friend...

    $104 (Avg Bid)
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    6 bids

    Using LabVIEW, FPGA & RT softwares, I need a data logger with cRIO-9047 chases for following modules. 1) 9205 2)9237 3)9232 4)9361 5)9467 I want to log data in RT (FPGA) at 10Khz for no more than 3 minutes. Two Load Cells, One Accelerometer, linear displacement through encoder, Trigger input by some switch, Speed tracking. After recording data I want to analyse it specially Accelerometer dat...

    $665 (Avg Bid)
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    17 bids
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    FPGA Bode Designer for Real-time application

    $1605 (Avg Bid)
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    5 bids

    Hi Chris, I looked over your profile and believe you may be the perfect fit for one or multiple projects we have. We currently have a chat translation app that is written natively for iOS and Android, and also works in the browser. We would like to utilize the same backend API, which uses sockets and uses Nodejs. I also believe the database is using mysql, but I'm not entirely sure. This is s...

    $3000 (Avg Bid)
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    Have a design that is synthesizable and works properly on FPGA (nexys video - artix-7 based). The clock is set via clock wizard, and I need to make it flexible without the need to regenerate bistream every time. The dynamic clock setting can be done via "sw" pins (nexys video has 8 sw pins on board). When new clock frequency is set, the expectation that design will reset and restart oper...

    $234 (Avg Bid)
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    17 bids

    I trained a ResNet50 model on 34 animal classes and on my Desktop PC and i got overall test accuracy 92.5%. after that i implemented a python code that takes this model and detects in real-time the animals classes, either from videos of trough a webcam. all i working well ok PC now i want to put this files on my PYNQ Z1 Fpga and to see it running there i installed tensorflow and keras on the pynq ...

    $119 (Avg Bid)
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    2 bids

    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

    $1118 (Avg Bid)
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    15 bids

    I trained a ResNet50 model on 34 animal classes and on my Desktop PC and i got overall test accuracy 92.5%. after that i implemented a python code that takes this model and detects in real-time the animals classes, either from videos of trough a webcam. all i working well ok PC now i want to put this files on my PYNQ Z1 Fpga and to see it running there i installed tensorflow and keras on the pynq ...

    $204 (Avg Bid)
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    6 bids

    I trained a ResNet50 model on 34 animal classes and on my Desktop PC and i got overall test accuracy 92.5%. after that i implemented a python code that takes this model and detects in real-time the animals classes, either from videos of trough a webcam. all i working well ok PC now i want to put this files on my PYNQ Z1 Fpga and to see it running there i installed tensorflow and keras on the pynq ...

    $133 (Avg Bid)
    $133 Avg Bid
    8 bids

    I trained a ResNet50 model on 34 animal classes and on my Desktop PC and i got overall test accuracy 92.5%. after that i implemented a python code that takes this model and detects in real-time the animals classes, either from videos of trough a webcam. all i working well ok PC now i want to put this files on my PYNQ Z1 Fpga and to see it running there i installed tensorflow and keras on the pynq ...

    $201 (Avg Bid)
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    2 bids

    Need to write VHDL program for Genesys 2 board for connecting a temperature sensor to xadc pin and display it in external LCD board

    $64 (Avg Bid)
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    8 bids

    I am looking for skilled programmer from Bosnia or Slovenia.

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    I am looking for designer to finish my logos and promotional images. He or She must have 3 years of experiences in design. Must be familiar with Adobe Photoshop, InVision, Principle, Framer ... Design sketches will be given in direct messages.

    $520 (Avg Bid)
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    E1. Registered users are not able to use the eway payment shows as invalid card but with guest users it is working. E2. Few design changes on the front end page, 1) the Logo should be increased 2) when the product is added to the Cart through mobile, the search and cart are getting overlapped and 3) remove the address from the contact us E3. During the registration, the mobile number validati...

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    I need to run some program (FPGA miner) on aws, unfortunately the problem is, its not compatible with the latest fpga ami from aws Here is the miner and the tutorial [login to view URL] its hdk source only can run on version 16.00 ami but its already being deleted by aws, and now the latest is version 18 ami (cmiiw) if somehow you can make it compatible again with version 18, i can pay up to 3...

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    I need to implement a true random generator on zedboard fpga. noise source will be ECG signal.

    $99 (Avg Bid)
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    13 bids

    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

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    Set up FPGA to mine Cryptonight v8. Consulation on which FPGA boards are best to buy.

    $641 (Avg Bid)
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    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

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    Need Signal Processing and FPGA based algorithm implementation expert.

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