A project to implement a calculator(ALU) in Verilog code using Quartus program I need a detailed report with state diagram and finite state machine I need one who can access my computer to teach me how to do the settings of the program also the Verilog code will be implemented on ALTERA board(DE2-115) also I need instructions of how I can run on
Project is to create C/C++ software to program Altera FPGA (MAX10) configuration memory from an embedded ARM processor using Altera JAM tools. The target device is MAX10 16M, and embedded CPU is Kinetis. The software must read a JAM file and program the FPGA configuration memory using the JTAG interface, which is bit-banged from the MCU pins. Deliverable
Microprocessor design project using system verilog in Modelsim and physical validation on Quartus Prime. I have started writing code for some of the blocks. The Register file, ALU and Instruction memory are nearly complete. Assistance needed in writing the remainder of the blocks: the instruction register, the micro controller unit, the W register,
Hi I'm looking for a good vhdl programmer to help me with a code. I'm supposed to bring in a simple logo, then i,m supposed to be able to display the logo on the center of a screen(using a vga connection) and my name on the bottom left corner while being able to flip the logo with a button on my fpga board the deadline is thursday. thank you. I have
We are working on an FPGA based doppler flowmeter with a custom PCB. At the moment, we are in the process of modeling algorithms using raw data recording in Matlab. This freelancer will be tasked with coordinating with the DSP engineer to design and implement changes from the Matlab models into our custom PCB, which Cyclone IV based. There is an existing
Project requirements will be provided after talking.
I have a digital input measurement signal, 0 ~...ZCU102 PL side RTL and bit file, Petalinux Image and drivers. 3. Remote support, to set up the whole system. 4. A block diagram and a brief explanation about your RTL code. Verilog is preferred. Please in the proposal, let me know how long would the project take and how much would you ask to build it.
Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read
I am enclosing description in the files.
Document with full requirements will be shared once discussed with person up for the job. Verilog code in top down design for a 4-bit ALU. A test bench will be needed to test design and needs to be able to program DE0-CV FPGA board to implement the full design.
Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.
Hello, I found your name in some Verilog source code that another freelancer (Linguang L.) apparently sub-contracted. (Reading data from a PYTHON5000 image sensor). I'm impressed with the work and was wondering if you'd be interested in doing some more, related work.
...games currently work fine, and one of the two modern flash-based cartridges on the market works correctly, but the other one does not. I believe that both of these carts are FPGA-based, and neither one of them is open-source hardware. I'm looking to hire someone to determine the root cause of the incompatibility, and to propose a circuit design modification
...do everything else on this project. I would provide the c-code so you could see how it writes a string of words to the RAM. I also have some VHDL code if you like that is about 98% there. A person skilled in VHDL and using Quartus should be able to write the code from scratch in about an hour or so. My hope is to read a large chunk of data from the HPS
i need someone teach me how to send and receive data from PCI using c# i have a project need to send and receive data from to FPGA by PCI using c# .net
I require following objectives, methods and methodologies, attached below I require simulation in MATLAB SIMULINK and hardware FPGA
Need verilog modules of VGA_Controller, Oscilloscope, Signal Generator, CDMA Transmitter, CDMA Receiver. The Signal Generator should be generating chips using Walsh Generator.
I want to get VHDL code for Simulation of brain tumor detection on Xilinx ISE design suite and dump on fpga. Fpga available is Zedboard.
project include following 1. data received from uart 2. after samp...after execution, data send via uart for display 4. parallel receiving and transmission of data while execution of algorithm 5. design block level diagram 6. test bench code in Verilog 7. project should implement on zedboard [login to view URL] code explanation (internal operation) is required
...need an assembly MIPS programming language program for demoing my project that did in system verilog language. It should not be more than 250 lines of codes in MIPS and it could be a Maze or Pack Man or another idea depending on the mentor. I will demo this on FPGA that already have these works and files already. here is some description of the task. Every
A verilog module shall be generated, that reboots a 7 series FPGA. It shall be compatible with all 7 series FPGAs, but at least with the following: - XC7A200T-2FBG676C - XC7K160T-2FFG676I - XC7K325T-2FFG676I The module will be tested on existing hardware, which uses master SPI x4 boot mode. The module input should be: - clk - up to 160MHz - reboot
An upload of a song is done from computer to Zybo by using a Wifi Pmod and audio processing operations like low-pass and band-pass filtering using FIR filter with adjustable cut-off frequency and bandwidth will be done on Zybo. The processed audio will be played using audio codec and necessary options will be displayed on a OLED Pmod for selection.