Fpga jobs

...PCIe endpoint (e.g., a Wi-Fi adapter). The card provides transparent passthrough of the endpoint device to the host system, while embedding an FPGA-based DMA engine capable of bus mastering, memory injection, and packet manipulation. Control of the DMA engine is performed via the PCILeech software suite, enabling flexible direct memory access operations. Functional Blocks 1. PCIe Passthrough Bridge • Provides a transparent PCIe x1 interconnect between the host computer and the attached endpoint device. • Maintains compliance with the PCIe protocol to ensure the endpoint is enumerated by the host as if connected directly. 2. FPGA Subsystem (AMD/Xilinx FPGA) • Implements custom PCIe cores for bus mastering and DMA transfers. • Supports injection of...

...PCIe endpoint (e.g., a Wi-Fi adapter). The card provides transparent passthrough of the endpoint device to the host system, while embedding an FPGA-based DMA engine capable of bus mastering, memory injection, and packet manipulation. Control of the DMA engine is performed via the PCILeech software suite, enabling flexible direct memory access operations. Functional Blocks 1. PCIe Passthrough Bridge • Provides a transparent PCIe x1 interconnect between the host computer and the attached endpoint device. • Maintains compliance with the PCIe protocol to ensure the endpoint is enumerated by the host as if connected directly. 2. FPGA Subsystem (AMD/Xilinx FPGA) • Implements custom PCIe cores for bus mastering and DMA transfers. • Supports injection of...

I have a completed research manuscript in the field of post-quantum cryptography's (PQC) hardware-software co-design on FPGA. The research, methodology, data, and results are fully complete. I need a professional academic writer/editor to rewrite the entire manuscript text while preserving the original technical meaning, then ensure it passes AI detection and plagiarism checks. I will provide **text only with references**—no figures, tables, algorithms, or equations. These elements are finalized separately and do not need editing. I am ready to supply the current manuscript (around 11,000 words plus references) and can answer field-specific questions quickly to keep the turnaround smooth. Scope of Work 1. Full Manuscript Rewriting & Academic Language Editing Rewrit...

...complete M.Tech-level project in the domain of Embedded Systems — from concept to implementation to documentation — that is also suitable for publication in a reputed conference. Scope of Work: The selected freelancer will be responsible for the following: 1. Project Development Propose a novel or improved project idea in the Embedded Systems domain (e.g., IoT-based systems, RTOS applications, FPGA-based design, sensor networks, edge AI on microcontrollers, wearable health monitoring, smart agriculture, or similar). Complete hardware design/simulation and software/firmware development. Deliver fully working source code, circuit schematics, and a prototype demonstration (physical or simulation-based). Provide a detailed project report following standard academic form...

I am building a gaming-focused DMA solution that pairs custom FPGA/PCIe firmware with a Windows host application capable of safely reading live game memory—specifically for first-person shooters running on Windows 10 and Windows 11. The hardware side must be compatible with KMbox-style boards (or a comparable PCIe DMA card), while the software side needs an intuitive UI and a clean, well-documented API so additional tools can hook in later. On the firmware front, you’ll write HDL that handles high-speed memory acquisition, exposes a secure command set over PCIe, and keeps all traffic indistinguishable from ordinary bus activity. Solid knowledge of USB/PCIe link training, BAR mapping, and DMA engines is essential. The host application should be written in modern C++ or C...

I’m looking for a seasoned digital-logic professional who can step into my lab workflow, quickly understand the design challenges on my bench, and guide me from concept through verified implementation. The immediate need is flexible: you might end up drafting fresh schematics for a small FPGA-based subsystem, debugging timing faults in an existing logic chain, or simply showing me how to streamline test-bench simulations so I can spot issues earlier in the cycle. Your familiarity with tools such as MATLAB, LabVIEW, or VHDL/Verilog will be invaluable—feel free to lean on whichever environment you know best as long as it gets us to reliable, reproducible results. I’ll share all current documentation, measurement data, and constraints as soon as we connect so you c...

I need custom firmware for a PCIe-based DMA card so a second PC can attach to my Windows gaming rig, read or alter memory, and feed data back—yet look to both Windows and Fortnite’s anti-cheat as nothing more suspicious than a standard IDE ATA/ATAPI controller. The core goals are: • Mask all DMA activity and device signatures so common anti-cheat sweeps find only an ordinary storage controller. • Keep full, low-latency read / write access to physical memory from the host PC. • Allow on-the-fly interception or modification of data in transit when required. You’re free to start from an existing open-source project (e.g., PCILeech-compatible hardware) or write bare-metal code, as long as the finished image flashes cleanly to the card and survives stres...

FPGA RF transceiver design ,

TCD1304 CCD Sensor FPGA Project I am looking for a skilled freelancer to assist me in designing a TCD1304 CCD sensor FPGA project. The project requires the following: Sensor read the value of every pixel and creates a two dimensional array with the pixel number starting with the value above the threshold and the number of pixels above the threshold. 0-[0,0],1-[0,0]..112-[0,0],113-[345,20],114-[345,25],115-[345,30],116-[345,35]...311-[345,200],312-[345,205],313-[0.0],314-[0,0] The above data gives like Triangle image from the left position from 345, and top position can be 113 based on trigger. Also it says 312 is end position of the mark. From the above details, we are looking a FPGA solution that read the data from CCD Sensor and store approach 32Mb data then p...

I'm seeking an experienced FPGA developer who can assist with design and development, specifically in HDL coding, using both VHDL and Verilog. Ideal Skills and Experience: - Proficiency in both VHDL and Verilog - Strong background in FPGA architecture - Experience in integrating and interfacing FPGAs with other systems - Ability to test, debug, and optimize designs Please provide relevant project experience and a brief portfolio. Looking forward to your bids!

...Analysis (25% Commission) Budget: Commission-only. $0 upfront. You get 25% of every client you bring. Description: I need a sales partner to bring me clients. I do high-end supply chain risk analysis for space and defense: SPOF identification Monte Carlo disruption modeling Geopolitical scenario planning Supplier concentration analysis My work is proven. I have sample reports showing rad-hard FPGA concentration risk (48% market share, $890M disruption impact) and reaction wheel dependency mapping (38% of Western satellites affected). Target clients: Small defense contractors (50–500 employees) Space startups (post-Series A) Aerospace consulting firms Space insurance underwriters Private equity (defense/aerospace focus) Services to sell: One-off reports: €...

...evaluation and risk controls. Here’s what I have in mind: the quantum side tackles portfolio state-space exploration—think QAOA, VQE or amplitude-estimation—while TensorFlow / PyTorch models learn micro-structure patterns from live tick data and route only the most promising parameter sets back to the gate model. Latencies must stay sub-millisecond from signal to order, so a coherent design for GPU–FPGA–QPU orchestration is essential. Deliverables • A documented architecture diagram showing data flow between classical AI, middleware, and the chosen quantum SDK (Qiskit, Braket or similar). • Clean, modular Python code with C++/CUDA kernels where latency demands it, fully containerised for reproducibility. • Back-test and forward...

...updated design files (Altium or KiCad preferred), annotated schematics, and a concise report showing the projected performance gains plus any trade-offs introduced. Please highlight relevant projects you’ve done in hardware optimisation, especially if they involved tight timing budgets or high-speed buses. If you have your own test methodology or simulation tools (e.g., SPICE, SignalIntegrity, or FPGA prototyping) let me know; I’m open to integrating them into the workflow....

I need an experienced FPGA programmer to assist with a data processing application. Key Requirements: - Proficiency in at least one of the following FPGAs: Xilinx, Altera, Lattice - Expertise in data processing applications - Familiarity with VHDL, Verilog, or SystemVerilog Ideal Skills and Experience: - Proven track record in FPGA programming - Strong background in data processing algorithms - Ability to work with various FPGAs and HDLs Please provide relevant experience in your bids. We need to develop ethernet hub in fiber optic 2 ports , and 16 SPI for chip led controller using data and clock . SPecia Ethernet protocol defined by us.

...side: define an architecture that can see each chip as stacks move, bets slide, and pots grow, then pass clean data to the software team through a simple API or wired interface of your choice. Key expectations • Robust HF antenna array layout sized for a poker table, including multiplexing strategy to handle >100 simultaneous tags without collisions or dead zones. • Reader, controller, and MCU/FPGA selection with justification, full schematics and PCB files (Altium, KiCad, or similar). • Tag specification sized for standard casino chips, with guidance on orientation tolerance and shielding. • Firmware outline or example code that streams tag UID and RSSI fast enough for smooth betting actions. • Bill of materials, power budget, and wiring harn...

PCB DESIGN with these or better components placement Processor & Memory Main SoC NXP iMX8M Plus — Quad Cortex-A53 1.8GHz + Cortex-M7 800MHz Safety MCU TI TMS570LS3137 — dual-core lockstep Cortex-R4F, SIL-2 certified Diag FPGA Lattice MachXO3LF-9400 — in-situ verification logic, <2ms latency RAM 4 GB LPDDR4, ECC enabled, 1600 MT/s Flash 32GB eMMC 5.1 (AES-256-XTS) + 128MB QSPI NOR boot Wireless MCU ESP32-S3 co-processor (Wi-Fi 6) Sensor Specifications Temperature PT1000 ±0.05°C (primary), DS18B20 ±0.5°C (backup), NTC (tertiary). Range: −40 to +150°C Humidity SHT45 ±1.0%RH + HDC3020 ±1.5%RH. Range: 0–100%RH, 0–85°C Pressure MS5837-02BA 0–2bar ±0.05%FS + MS5837-30BA 0–30bar (secon...

...QUBO/Ising workloads for Logistics, Finance, and Cyber-Intelligence, and I’m open to engaging specialists across several tracks: • ML Engineer – craft graph neural networks and matrix-compression pipelines that translate complex optimisation problems into sparse, hardware-friendly representations. • FPGA Engineer – write VHDL/Verilog kernels for AWS F1, pushing the solver to micro-second latency. • Backend Architect – design a high-performance API layer in Go, Rust or Python that orchestrates FPGA instances, manages job queues and exposes REST/gRPC endpoints. • Cyber-Security Expert – conduct cryptanalysis and network-intelligence research to harden the solver and uncover new optimisation attack vectors. If you ...

I am building a Verilog-based, real-time Sobel edge detector that streams video from an OV7670 camera to a monitor over VGA on a Nexys A7-100T board, all within Xilinx Vivado. The architectural concept is clear, yet the project’s success now depends on rigorous simulation, validation, and concise documentation suitable for an academic submission. Your main focus will be designing an efficient test and simulation strategy: self-checking test-benches, frame-level functional coverage, timing verification, and any other diagnostics that prove the design meets real-time performance. I am open to whichever simulation environment you consider best—whether you stay inside Vivado’s integrated simulator or introduce ModelSim, Verilator, or another workflow—provided it integr...

...combination; ModelSim, Vivado, Quartus, or Logisim waveforms are all acceptable. • Brief, well-commented documentation so I can present the design during our tutorial session and explain each decision made along the way. If you see opportunities to streamline logic or suggest alternative gate technologies (TTL, CMOS, FPGA primitives), feel free to include them—learning the optimisation process is part of the exercise. Once we’re confident in simulation, I’ll move the design onto a small FPGA board for the laboratory component, so pin assignments or constraint files would be a welcome bonus. Deliver everything as a zip containing the schematic/HDL files, simulation testbench, resulting waveforms, and a concise PDF report. I’m ready to get st...

... • MCU: NXP RT1062 (any close RT family device is acceptable) • ADC: AD9214 on the same 12-bit parallel bus • FPGA: Intel Cyclone 10 LP 10CL006YE144C8G, programmed over JTAG with Quartus 18.1 through a USB Byte Blaster II Scope of work – Translate the legacy Altium sheets to the new silicon, preserving all high-speed routing constraints. – Verify clocking, power rails and pin muxing for the RT and Cyclone 10 combo. – Hand-off updated Altium files, BoM and any design notes needed by our firmware team. – Drive the first-article bring-up: JTAG access, SDRAM memory test, LCD frame buffer check, ADC capture integrity and seamless data hand-off to the FPGA fabric. Acceptance The job is considered complete once the new boar...

...a synthesizable, timing-clean Verilog implementation of the classic MUSIC (Multiple Signal Classification) algorithm that can estimate the direction of arrival of one or more narrow-band signals received on a uniform linear array of four antennas. The end use is a radar front-end, so accuracy takes priority over latency or power. Scope • Design the fixed-point signal-processing chain on an FPGA (I am currently working with Xilinx Series parts; feel free to suggest an equivalent if it helps meet timing). • Implement covariance matrix formation, eigen decomposition and the pseudospectrum peak search entirely in hardware; no soft-core processors or external DSP chips. • Include provisions for array calibration coefficients so the design can be tuned on-site. ...

...considerations (EMI, safety). Your past projects should show that you have already solved comparable challenges and can back it up with real-world test data. Key deliverables (in discrete form): • Schematic and BOM with industrial-grade components • Magnetics design files and calculations • PCB layout (Altium, KiCad, or similar) optimized for thermal paths and low noise • Digital control firmware or DSP/FPGA logic, fully annotated • Simulation files (SPICE, PLECS, or equivalent) validating efficiency and THD • Prototype test report confirming output quality, protection triggers, and thermal behavior After awarding the project I’ll share the final power rating, enclosure constraints, and any branding-specific compliance marks so we can lock do...

I need clean, well-documented VHDL that implements a set of simple digital circuits on an FPGA. The task sits firmly in the Digital circuits design space—no signal-processing tricks or embedded firmware layers—just straightforward gate-level logic and a few flip-flops brought to life in hardware. Here is what I expect: • VHDL source files for each module • A small, self-checking testbench that runs in ModelSim/Questa or an equivalent simulator • Clear synthesis-ready code that fits easily onto a mid-range Xilinx or Intel development board (the exact board can be generic; resources should stay minimal) • A short README outlining how to simulate, synthesize, and pin-map the design Because the scope is intentionally simple, I value concise code,...

I need a list of all companies using FPGA chips and all FPGA developers and their team managers worldwide (excluding mainland China, Russia, Iran) that have profiles on platforms such as LinkedIn. The spreadsheet should contain two sheets, one for companies and applications, one for developers and team managers. The first sheet shall list: Company name, product line name, product line category, product line URL, market segment (industrial, medical, aerospace, defense, test&measurement, wired comms, wireless comms, accademia, consumer, automotive, broadcast, emulation, finance, datacenter, scientific), product line location (city and country), estimated revenue. The second sheet shall list induvidual FPGA developers and their managers: Name, job title, is team manag...

I am working on Experiment 4 for a RISC-V datapath design using SystemVerilog in Xilinx Vivado (simulation only). The project requires implementing the following RTL modules from scratch according to the RISC-V ISA specification: 1. IMMED_GEN This module must generate all five RISC-V immediate formats from instruction register bits [31:7]: • I-type • S-type • B-type • U-type • J-type Each immediate must be correctly sign-extended and aligned according to the official RISC-V bit-field definitions. 2. BRANCH_ADDR_GEN This module must compute the target addresses for: • JAL • JALR • Conditional branch instructions by adding the appropriate immediate value to the base PC value and ensuring correct address alignment. --- CURRENT ISSUE: My previo...

I’m updating the firmware for an STM32-based design and need an experienced C++ developer who is comfortable inside STM32CubeIDE. The codebase already compiles and runs on the microcontroller, but several features still require clean, well-structured implementation, performance tuning and thorough testing directly on the hardware. You’ll be working exclusively with STM32 microcontrollers; no FPGA or other targets are involved. Please be ready to pull the current CubeIDE project from my repository, build it as-is, and then extend it in C++17 (or later) while respecting the existing HAL layer and project structure. Deliverables • Updated CubeIDE project with the new or fixed functionality fully integrated • Clear build instructions and a short change log so...

We are seeking an experienced Zynq UltraScale+ FPGA engineer to assist with the bring-up of our ZCU104 board, focusing on camera interface and testbench development. The ideal candidate will have hands-on experience with FPGA design, verification, and debugging. You will be responsible for ensuring the functionality of the camera interface and developing a comprehensive testbench. Knowledge of embedded systems and familiarity with relevant development tools is crucial for this role.

I’m updating the firmware for an STM32-based design and need an experienced C++ developer who is comfortable inside STM32CubeIDE. The codebase already compiles and runs on the microcontroller, but several features still require clean, well-structured implementation, performance tuning and thorough testing directly on the hardware. You’ll be working exclusively with STM32 microcontrollers; no FPGA or other targets are involved. Please be ready to pull the current CubeIDE project from my repository, build it as-is, and then extend it in C++17 (or later) while respecting the existing HAL layer and project structure. Deliverables • Updated CubeIDE project with the new or fixed functionality fully integrated • Clear build instructions and a short change log so...

...existing electrical interfaces to the MYIR board unchanged and minimizing or avoiding FPGA/firmware changes as much as possible. Scope of Work (High Level) - Integrate two RF transmit chains on one board - Use a shared reference oscillator and PLL for both RF paths - Replace discrete RF filters with compact off-the-shelf RF filters - Replace legacy power regulators with modern, small LDOs - Add RF routing options: - Combiner for both RF outputs - Splitter to provide up to three RF outputs - Focus on size reduction and clean, manufacturable design Key Constraints - MYIR Zynq-7020 board and its connectors remain unchanged - Signal interfaces to the Zynq better stay compatible with the existing design - FPGA and software changes should be minimal or not required - PCB manuf...

...Tech academic projects in the Embedded / ECE domain for Indian universities. We are looking for one reliable freelance Embedded Systems developer for long-term, project-wise collaboration. This is not a full-time job. Work will be assigned per project. Scope of Work Develop Embedded / ECE hardware or simulation-based projects Support domains like: Embedded Systems, IoT, ARM / Microcontrollers FPGA / VLSI (optional) Control systems / Sensors / Automation (as applicable) Deliverables per project: Working code / simulation / hardware logic Result screenshots / output proof Project report content (chapter-wise) Project PPT content IEEE conference paper draft Scopus journal extended paper draft Support 1–2 rounds of revisions based on guide/reviewer comments Requ...

...Microcontroller and embedded targets rotate between Arduino-based boards, Raspberry Pi modules, and mid-range FPGAs, so comfort switching among those platforms is essential. Core expectations • Design or refine circuits and document the rationale behind every component choice • Build and verify MATLAB/Simulink models that correlate with hardware behaviour • Prototype on Arduino, Raspberry Pi or FPGA as the problem dictates and capture results in a concise technical report • Deliver well-formatted reports (Word or LaTeX) that include schematics, simulation plots, and test data I review drafts collaboratively, offer rapid feedback, and release milestones as each design, simulation, and report section is accepted. If you graduated recently, have the abo...

I need a seasoned PCB designer located in Pakistan who can take a concept right through to production-ready files. The boards you create must interface reliably with Arduino, Raspberry Pi, and FPGA modules, so familiarity with their pinouts, signalling levels, and power budgets is essential. You’ll start by translating my functional requirements into clear schematics, then handle the full PCB layout, component selection, and DFM checks. I expect well-organised source files plus manufacturing outputs—Gerbers, drill files, pick-and-place, and an accurate BOM—with every revision traceable. If you prefer Altium, KiCad, Eagle, or OrCAD that’s fine; just let me know which environment you’ll use so I can open the files on my end. Because these boards may...

I'm seeking an experienced FPGA developer to help debug logical errors in existing VHDL code for a Lattice Semiconductor MachX03 development board. Key Requirements: - Expertise in VHDL - Experience with Lattice Semiconductor FPGAs - Strong debugging skills, especially with logical errors Ideal Skills and Experience: - Proven track record in FPGA development and debugging - Familiarity with MachX03 specific features and tools - Ability to provide clear, concise solutions and documentation Looking forward to your expertise!

...presentation-ready diagram that shows our network architecture in a way that looks great on a slide deck. The look should stay firmly in the minimalistic camp—simple lines, flat colours, no shading—yet still feel polished and professional. Please represent these entities with matching iconography: • Cell tower • RF probes • FPGA module • Neural-network processing block The flow is straightforward: signal originates at the cell tower, passes through the RF probes, feeds into the FPGA for conversion, and ends up in the neural-network section. Arrange the elements so that this path is obvious even to a non-technical audience. Deliverables • Editable source file (AI, Figma, or SVG) • High-resolution PDF or PNG, 16:9 ...

I need an expert in low-latency data acquisition systems. We are utilizing FPGA-based DMA hardware to interface with a running application. I require assistance in mapping internal data schemas and establishing reliable logic paths for an external Python controller. The ideal candidate has experience with LeechCore or similar hardware-interfacing libraries and understands C++ memory management.

I am assembling a 30-member core team to take India f...Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring; they matter. Key acceptance criteria • Architecture spec frozen within 60 days of team formation • First FPGA bring-up by month 6 • Tape-out-ready GDSII no later than month 12 If you’re passionate about putting India on the global semiconductor map and ready to own a slice of ...

I am assembling a 30-member core team to take India f...Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring; they matter. Key acceptance criteria • Architecture spec frozen within 60 days of team formation • First FPGA bring-up by month 6 • Tape-out-ready GDSII no later than month 12 If you’re passionate about putting India on the global semiconductor map and ready to own a slice of ...

Your task is to code an RGB to MIPI DSI pipeline in a Lattice LIF-MD6000 FPGA. The objective is to simply succesfully initialize and show a video output on a specific VR-type MIPI DSI display of which the full datasheet will be provided. The display requires a specific initialization procedure that includes DCS and Manufacturer commands. The display can be used in both 4x2 data lanes or 4x1 data lanes by using Vesa DSC compression. The latter shall be used and a compression layer shall be included in the pipeline. The pipeline shall use as little LUTs and resources as possible, and to do so it shall use the hard d-phy interfaces included in the FPGA. A basic test pattern generator may be used to show functionality for the video output.

...brief is image-processing: sharper live visuals, instantaneous frame-by-frame analysis, and on-screen flags whenever the algorithm spots a potential anomaly. All processing must happen in real time without introducing perceptible latency to the surgeon’s view. My current hardware outputs standard HDMI and records to DICOM, so your code should sit either between the camera head and the display (FPGA, GPU box, or high-performance PC is fine) or run as a software module on the workstation already attached to the scope. OpenCV, CUDA, TensorFlow, or similarly robust libraries are welcome—just keep licensing constraints clear. Deliverables • Executable or deployable source that enhances image clarity, performs real-time analysis, and triggers automated anomaly detect...

I am seeking a multi-disciplinary expert or a small team to assist in a high-fidelity hardware research project focused on PCIe device emulation and DMA-based memory forensics. The goal is to develop a custom FPGA-based solution that can perfectly mimic a legitimate consumer PCIe device (e.g., Network or Storage Controller) to pass low-level system integrity checks. Key Responsibilities: Emulation (FPGA/Verilog): Develop custom firmware for an Artix-7/35T/75T FPGA board to emulate a real-world donor device's configuration space and TLP behavior. Development (C/C++): Create a high-performance Windows/Linux driver for direct memory access via the PCIe bus, ensuring stability and low latency. Analysis: Design a system to read and analyze specific application me...

FPGA + SDR (ADRV9009) System Development – ZC706 Platform Project Description We are looking for an experienced FPGA / SDR engineer to develop a complete ADRV9009 + Xilinx ZC706 based SDR system. The project includes RX/TX signal processing, FPGA firmware development, Linux integration, and Ethernet-based control and data streaming. Hardware Platform • FPGA Board: Xilinx ZC706 Evaluation Board • RF Front-End: Analog Devices ADRV9009 SDR Development Board • System Type: Single integrated ADRV9009 + FPGA SDR system Interfaces • JESD204 (ADRV9009 - FPGA) • Ethernet (ARM/FPGA - PC) RX (Receiver) Requirements • Capture RF signals with 200 MHz instantaneous bandwidth • Configurable parameter...

We are looking for a proactive and versatile assistant to support operations, travel coordination, project management, and documentation activities within an FPGA and embedded systems company. This position is primarily remote, but occasional in-person visits to our main offices or participation in business trips within Europe (mainly Italy and Germany) will be required. You’ll collaborate directly with the company founder and CEO, helping streamline daily operations, audits, and international coordination. Key Responsibilities Travel & logistics: organize flights, hotels, and transfers for business trips; manage travel expenses and reimbursements. Project coordination: track tasks, milestones, and deadlines; assist in preparing reports and follow-up summaries. Documen...

I have an OLED panel wired directly to a Xilinx-based FPGA design and the existing display driver is outdated.

I’m building an integrated computer system and need a specialist to take full ownership of the hardware side of its networking component. The objective is straightforward: create a router/switch that delivers markedly higher throughput than off-the-shelf options. You will translate my performance targets into a workable design, choosing the right switching ASICs or FPGA packet engines, laying out a high-speed, signal-integrity-friendly PCB, and planning for power, thermals, and EMI from day one. Experience with multi-gigabit Ethernet PHYs, SERDES routing, and design tools such as Altium or KiCad will be invaluable—we’ll lean on those skills to keep iterations to a minimum and get to the lab quickly. Deliverables I expect: • Complete schematics ready for revi...

...India that still needs its very first breath of life, and I want Zephyr running on it. The immediate goal is classic board bring-up: get the SoC to boot into Zephyr cleanly, prove that the console works, show me the GPIOs toggling, and hand back a minimal yet reproducible reference design so future work can build on top of it. Here’s what I expect from you: - Riscduino riscv based soft SoC on FPGA, need bring-up zephyr on this platform • Create or adapt the Zephyr board definition (device-tree, Kconfig, defconfig, pinmux, etc.). • Deliver a patch series I can upstream or re-apply, together with concise build and flash instructions that work on a fresh clone of Zephyr and the RISC-V toolchain. Acceptance is simple: I flash the image exactly as documented, Z...

...configure the Xilinx FFT IP for 8192 points, wire it to the chirp stream, and handle any required data-format conversions or hand-shaking. • Provide timing-compatible top level, constraints, and a self-checking test-bench that sweeps the chirp, captures the FFT output, flags the peak bins and dominant frequencies. Acceptance is straightforward: when I run the supplied simulation and then program the FPGA, I should see the chirp transition cleanly across the stated band and the FFT output highlight the correct moving peak without spurs or dropped samples. More projects to follow for right skilled engineer....

Code simulator and description for Basys 3 fpga board

...profiles should show hands-on success with real-time video streaming, image recognition, and advanced video compression while working close to the metal on custom hardware. Because these products live on constrained platforms, I’m especially interested in candidates who can pair the video know-how with strong embedded systems expertise, practical machine-learning integration, and, where relevant, FPGA development for acceleration. What I need from you is a curated bundle of CVs—each one clearly demonstrating the above skill mix, employment history that proves mid-level depth (roughly 3-7 years), and concise notes on why the candidate fits. Feel free to include any additional screening insights you believe add value. I’ll review the first batch, provide feedba...

I’m building a video pipeline on an Artix-7 XC7A200T board that carries two ADV7611 HDMI inputs and one SiI9134 HDMI transmitter. I need a complete Vivado project that captures 1080p video from both ADV7611 receivers, performs basic in-FPGA signal processing (frame buffering, colorspace conversion or simple image filter—whichever is cleanest to showcase the path), and then drives the SiI9134 so the processed stream displays correctly on an external monitor. The project must be written in synthesizable Verilog or VHDL, use the latest Vivado tool-flow, and include: • Top-level RTL connecting the ADV7611 I²C, video, and clock lines to the SiI9134 interface on the XC7A200T • A timing-clean 148.5 MHz pixel clock domain plus any required gearboxes or FIFOs f...

Also, have to record a short demo, and write a simple report.