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    1,101 hyperlynx xilinx ddr2 jobs found, pricing in USD

    I need to implement an Ed25519 Algorithm in Verilog for FPGA implementation that can properly simulate on Xilinx Vivado Design Suite. The complete algorithm code is already available in C language and I want to convert it into Verilog. Link:

    $231 (Avg Bid)
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    8 bids

    I am looking for an electrical engineer who can work on FPGA TEST Board design. The project is to design FPGA TEST Board for XC7VX690T-2FFG1157I chip. We need power supply connectors as Banana jack and JTAG, UART, and SPI flash, and other decoupling capacitors and resistors. We just need simple workable Sch and PCB design wit optimal design. The candidate should have rich experience in FPGA PCB design using Altium.

    $30 / hr (Avg Bid)
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    I have a Xilinx KV260 board. Would like to develop a small robot project based on Vitis AI or PYNQ libraries. Need some simple documentation for education purposes. Be able to communicate.

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    I want the project to be done on Xilinx using Verilog/VHDL where 64bit binary counter using prescaled block can be created.

    $114 (Avg Bid)
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    Hi, I need to create a Xilinx Petalinux project with a custom driver to control a led in Ultra96v2 board. I just need to be able to turn/off a led in Petalinux using a driver.

    $235 (Avg Bid)
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    HDL coding using Xilinx ISE 14.7

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    ...acceptance of work and start of project. 2. Begin by adding PCIe BAR read logic for BAR 0 & 1. Including code snippet to do this and verification at client end on the Screamer board. The design will be able to read some predefined values via BAR reads. This will also include bring up of AC701 if required to debug hardware at my end. Beginning with work based on simulation results and documentation from Xilinx. Will try to provide this before the holiday period outlined below but can't be guaranteed. 3. Translate the driver source code header file with its comments into HDL that responds based on the comments in that file. Integrate this into PCI leech. Provide code snippet. 4. Final code and documentation hand off, address any outstanding issues. Project will begin with...

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    ...mathematical algorithm to implement each step and phase which Comply with VIVADO HLS. Compare the result with the most recent references.(Analysis) the cloud computing environment is as you want ( Amazon , cloud Hardware ( EC2 F1) ) . It should tset the code in C++ and VHDL then compare them with Accuracy and time Vivado is belong to Xilinx and I do not need any implemantation so you can choos any chip or just do the test case the focus on simulation. The Xilinx Vivado HLS tool is one of the available high-level synthesis tools in the market. The main idea behind Vivado HLS is transforming a language specification design,into an RTL designed by converting it into Verilog or VHDL to accelerate and optimize implementation of algorithms for FPGA boards. ...

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    Please do NOT bid if you do not have the following experience This project requires an Experienced Embedded Programmer. 1. Prior experience in writing Interrupt Service Routines in Linux is a must 2. Prior experience with YOCTO is a must 3. Prior experience with Xilinx xDMA is a must 4. Prior experience with PCIe Interface is needed. 5. Familiarity with RISC-V architecture is a plus.

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    I need an expert in Xilinx SoC-FPGA to design a specialized accelerator for computer vision algorithm. The key is to train and optimize the network and implemented efficiently into hardware. Should be knowledgeable of PyTorch, Vivado, HLS, C++.

    $39 / hr (Avg Bid)
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    Hello I'm looking for experienced engineer that will implement PCIe BAR interface to my private project forked for pcileech Project is developed on FPGA Chipset: Xilinx 7 Series XC7A35T on ScreamerM2 r03 This can be a basic implementation in the firmware (when it returns zero or unsupported request) If you would be interested in this work, I can provide more details about project and revenue for this work.

    $500 (Avg Bid)
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    I need a FPGA programmer to build a mining solutionfor mining Ethereum with a Xilinx U250 in azure vm NPsV1 os ubuntu

    $608 (Avg Bid)
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    I need a FPGA programmer to build a mining solutionfor mining Ethereum with a Xilinx U250 in azure vm NPsV1 os ubuntu

    $550 (Avg Bid)
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    ...programming voltages required on each pin, per manufacturer spec 3. Full MS-CAN, K-line, J1850 and DoIP required, per manufacturer spec 4. Interface needs to centre around an FPGA, to allow for future feature upgrade. FPGA firmware code to be written in either SystemC (preferred) or VHDL. In either case, needs to be fully documented. 5. XC7Z020-1CLG400C FPGA (or better, from the same series) from the Xilinx lineup is to be used. Verification will be carried out on the Digilent Zybo Z7 Board. Necessary drivers and bring-up to be provided as a set of Yocto packages B. Software/Firmware: 1. Host device for the interface detailed above shall be a BeagleBone Black device (), with the interface provided as a Cape, following the hardware interface specification for

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    Hi Dmytro P. Hello. I am looking for FPGA programmer to create Bitsream + software for mining Ethereum on Xilinx Alveo U200 . If Ethereum mining is not possible on Alveo U200 board due to slow memory – looking for the possibility to create software able to accelerate already existing GPU hash rate. I can give you remote access in order to check your software while creating Or as an alternate solution if non above is possible – TONCOIN Bitsream + software Will wait for your reply, Dmitrij

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    i need a tool used to mine ETH using FPGA (Xilinx Alveo U205). can you do?

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    Mining Setup needed for FPGA Xilinx Alveo U250 Deployment VM - Ubuntu18.04

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    Mining Setup needed for FPGA Xilinx Alveo U250 Deployment VM - Ubuntu18.04

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    Hi, I have one FPGA Xilinx Alveo U250 Deployment VM - Ubuntu18.04 I can't get it to work with any of the cryptocurrency mining software, as those apps don't see/recognize the card at the moment. I am 100% sure that this can work, just need to figure out how specifically or what else needs to be done here. I am not sure what I still need here, what driver or tweak is required, or whether we need to even write a custom code for the two to work together. Please contact me only if you know exactly what this is all about and in your application for the job, do your best to get my attention by mentioning how you plan to fix this for me. Plain applications with bunch of qualifications and past experience doesn't do much for me. Mentioning that you read my post here and...

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    My team and I are currently building a cryptocurrency mining farm. We are using specific devices, called: Xilinx Varium C1100 blockchain accelerator FPGAs. We want to be independent from other miners and no longer depend on their mining software and bitstreams. Therefore we are looking for a programmer who is experienced in FPGA design and is able to program a working miner for any cryptocurrency with the right bitstream. The Software will be written in: Xilinx’s Vitis™ development environment (C, C++)

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    The project is to program a Xilinx FPGA chip with the logic pre defined

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    I need specifical programm for f1 instance

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    Hi, I have one FPGA Xilinx Alveo U250 Deployment VM - Ubuntu18.04 I can't get it to work with any of the cryptocurrency mining software, as those apps don't see/recognize the card at the moment. I am 100% sure that this can work, just need to figure out how specifically or what else needs to be done here. I am not sure what I still need here, what driver or tweak is required, or whether we need to even write a custom code for the two to work together. Please contact me only if you know exactly what this is all about and in your application for the job, do your best to get my attention by mentioning how you plan to fix this for me. Plain applications with bunch of qualifications and past experience doesn't do much for me. Mentioning that you read my post here and...

    $500 (Avg Bid)
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    I have a Xilinx VHDL project. Only contact me if you can do VHDL programming in the Xilinx ISE Design Suite.

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    a PCI device inserted into computer "A" that is running Linux 64 bit and connected to an external computer "B" with a stan...Linux 64 bit and connected to an external computer "B" with a standard SATA cable, providing a dynamic/virtual SATA DISK to computer "B" On computer "A" communication with the "SATA device" is done over the PCI port - read/write blocks etc. I am thinking an FPGA chip with maybe LiteX cores for the implementation and maybe using some kind of PCI FPGA development card like the Dragon-E FPGA board Xilinx Virtex-5 Another option could be to create a standalone device based on FPGA that has a SATA device core and Ethernet core that just relays the disk "command" over the network to a client se...

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    Hi Mairaj Ali, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I need a cryptominer program for Xilinx fpga.

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    Looking for an expert in Xilinx FPGA-SoC Ultrascale+ with skills in HW/SW co-design of using HLS and Vitis for implemented and optimizing Deep Learning algorithms.

    $35 / hr (Avg Bid)
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    We need to test our Kadena protocols so we need somebody expert in stratum JSON and also in FPGA/miners application to modify it and make it compatible with out FPGA module to test if the protocol Kadena is working perfectly and it is efficient enough. The perfect candidate is a person who know stratum protocols and C++ plus have experience with VHDL communication protocol in particular Xilinx Bets is to have knowledge of this client for Kadena to test the difficulty on testnet PS. Please check this is the library to be changed

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    Need to implement Harris Corner Detector for corner detection using Verilog HDL and implement the same code using xilinx vivado.

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    I am updating the design of a FPGA board and would like to out source the layout phase. The board consists of the following key components: • FPGA - Xilinx zynq 400 ball device • RAM DDR3 • Ethernet • I2C 8 I2C slaves on two I2C ports • SPI interfaces to 4 SPI interfaces The design requires a flexi rigid PCB and I anticipate that the FPGA section will require 6 layers though the time critical nets will need to be located on the outer most layers. I am looking for a designer who will collaborate on finalising the schematics and will complete the PCB layout based on PBC manufacturers design tolerances and rules. There are be several of groups of tracks that need their lengths matched and impedance levels maintained.

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    We need to port to native c++ a KDA algo that is blake2s and verify that works (so that create nounce from work) and then port this to HSL verilog (xilinx) The code can be taken from CryptoPP or from this link: Taken from this library: Once the code is verified in C we need to test to see if we can generate nounce and confirmation and if possible optimize it

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    I have a Xilinx FPGA project and I would like to update it to use a newer Xilinx FPGA. The project can be found here: I need to convert this HDL from a Spartan 3A device to a Spartan 6 device: This project utilizes a ZPU GCC compiler to synthesize the project which is unique for some Xilinx FPGAs.

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    Hello, you've sent me a message earlier about a project in Xilinx and VHDL, are you still available?

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    I need a developer who can build a miner for sha256d algo (including bitstream) for u200 fpga’s FPGA’s are located in aws data center, We could give you a ssh or rdp connection to them.

    $17274 (Avg Bid)
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    Hi, I have one FPGA Xilinx Alveo U250 Deployment VM - Ubuntu18.04 I can't get it to work with any of the cryptocurrency mining software, as those apps don't see/recognize the card at the moment. I am 100% sure that this can work, just need to figure out how specifically or what else needs to be done here. I am not sure what I still need here, what driver or tweak is required, or whether we need to even write a custom code for the two to work together. Please contact me only if you know exactly what this is all about and in your application for the job, do your best to get my attention by mentioning how you plan to fix this for me. Plain applications with bunch of qualifications and past experience doesn't do much for me. Mentioning that you read my post here and...

    $320 (Avg Bid)
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    5 bids

    Goal is to develop the FPGA (Lattice, Xilinx, ...) based camera converter from MIPI CSI-2 to JPEG over SPI. We need the working prototype arounf end of february (2022) Deadline of the final version is the end of March. Project result must be the production ready PCB design. Key specifications are: 1. STM32 is connected to the FPGA: it receives the JPEG frames over SPI and controls the camera via I2C. FPGA triggers GPIO when new frame is completed. STM32 can do modifications on the camera settings and video stream. Additional tasks of the FPGA are the init-reinit of internal buffers, modules and stop video stream receiving cycle when MCU sends stop signal (using GPIO). In summary, FPGA must handle the situation when no input from the camera and the image parameters (e.g. resoluti...

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    Port design from Max10 FPGA to Xilinx Zynq

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    This job consists of implementing into a Xilinx Zynq three pipelines into vivado 2019.1: A phase lock loop using fixed point A frequency lock loop A delay lock loop Timeline: 3 weeks

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    Implement an FPGA-BASED ADAPTIVE NOISE CANCELLING SYSTEM according to the first paper and provide a full report of the works done. After that study available solutions for binaural rendering and extend the previous experimentation to other rendering solutions according to the second paper with a full report

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    i have Xilinx FPGA BCU/VCU1525 Card, i want to bit Stream for Ethereum Coin, and i have also vivado lab 2020,

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    Vhdl program to display digital clock using nexys 4 ddr in vga display. Vhdl not verilog. Using xilinx vivado

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    Hi there We need support with the implementation of programme (written in Python) to be implemented in PYNQ-Z2 (Xilinx). Please advise if you have knowledge of PYNQ-Z2 (Xilinx). Thanks

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    Hi there We need a freelancer with experience in the following task: Application programmed in Phyton to convert images in back and while to colour, and restore the image where needed. The application will be used and tested in PYNQ-Z2 (Xilinx). Thanks

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    I have a simple Xilinx project that would not take much time. I need it by the 3rd of November. Please see the attached document, and let me know if any more info is needed. Thank you

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    The project is to implement a GPS / Galileo signal tracking algorithm into the FPGA side of a Zynq 7020. A first algorithm has been already developed and validiated on Matlab. The scope of this job is Task-1.1 FPGA Design to convert the GNSS tracking algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-1.2 Validation of the VHDL design using 3D Aerospace pre-recording data on Zedboard Task-1.3(optional) Development of a Petalinux application for real-time implementation (v2019.1) Task-1.4 Provide a clean code with the associated documentation. Task-2.1 FPGA Design to convert the GNSS demodulation algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-...

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    Project need ethminer kernel(source and binary file) for xilinx u200. I want to program using vhdl/Verilog.

    $1500 - $3000
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    The project is to implement a GPS / Galileo signal tracking algorithm into the FPGA side of a Zynq 7020. A first algorithm has been already developed and validiated on Matlab. The scope of this job is Task-1.1 FPGA Design to convert the GNSS tracking algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-1.2 Validation of the VHDL design using 3D Aerospace pre-recording data on Zedboard Task-1.3(optional) Development of a Petalinux application for real-time implementation (v2019.1) Task-1.4 Provide a clean code with the associated documentation. Task-2.1 FPGA Design to convert the GNSS demodulation algorithms given in C++ by 3D Aerospace for to the FPGA (in VHDL) side of a Zynq-7020 using Vivado 2019.1 (baremetal) Task-...

    $32 / hr (Avg Bid)
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