Matlab verilog jobs

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    1,333 matlab verilog jobs found, pricing in USD

    ...to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not quite sure with the Verilog language

    $152 (Avg Bid)
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    11 bids

    ...hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience

    $187 - $560
    $187 - $560
    0 bids
    Verilog coding 6 days left

    Verilog code of Simplified DES algorithm

    $15 (Avg Bid)
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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $302 (Avg Bid)
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    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think t...any other sensors I haven't mentioned will work better? Therefore, I think we need some chat to find a solution before start working. FPGA: Xilinx Basys3 Language: Verilog HDL Software: Vivado 2015.4

    $181 (Avg Bid)
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    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    $137 (Avg Bid)
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    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

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    200418_Verilog 1 day left
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    $50 - $80
    Sealed
    $50 - $80
    4 bids

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    $388 (Avg Bid)
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    6 bids

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

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    Tcp sending on FPGA using verilog xgmii xilinx vivado

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    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

    $416 (Avg Bid)
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    more details will be given in the chat

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    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

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    Small project on computer architecture

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    I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated

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    I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools)

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    ...Language=English&CategoryNo=167&No=921) and 2. wiz830mj ([url removed, login to view]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes W5300 chip and sends some data to PC by TCP/IP. The solution should be verified by sending ascending numbers from 0 to 255(8 bits) in an endless

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    I need Verilog hardware description language expert. I need to modify two modules only: mips.v and mips-control.v. Details are in the attached file.

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