Online afghan verilog vhdl jobs jobs

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    3,305 online afghan verilog vhdl jobs jobs found, pricing in USD
    DSP48E1 help 4 days left

    Hi! I need some help with DSP48E1 verilog instantiation.

    $4 / hr (Avg Bid)
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    5 bids

    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

    $206 (Avg Bid)
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    11 bids
    I want clients 15 hours left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

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    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

    $19 / hr (Avg Bid)
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    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

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    7 bids

    Buyer Website Features: UI Design, UI Integration, Login/Signup, Homepage, Browse Categories and Sub Categories, Search for Products/Vendors etc, Listing of Products (Sort, Filter etc.), View Product Detail Page, Add to Cart, Cart Management, Checkout Management, Billing & Shipping Module, Payment Gateway Integration, My Orders, My Wish-list, Address Book, Review and Rating, My Profile, Setti...

    $1229 (Avg Bid)
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    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

    $499 (Avg Bid)
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    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

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    1 bids

    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

    $25 (Avg Bid)
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    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

    $28 (Avg Bid)
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    I need help with the structural in Xilinx. I will give you full details. Regards

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    24 bids

    ...am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

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    112 bids

    Hi, my name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the

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    1 bids

    verilog coding using putty or terminal. if you are interested i will give more information.

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    I want help with system Verilog coding. I have a working code that I want revised a bit.

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    9 bids

    Implement an AD2949 IC input block and some more

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    mtech Verilog project

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    looking for someone who can convert Open CL algorithm into FPGA Verilog project

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    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

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    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

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    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

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    21 bids

    ...to keep track of what jobs they are doing and how far they have progressed. I have an incoming purchase order that is a pdf file. I need the information taken from that purchase order and transferred to another document that displays the original information plus a few extra columns indicating a start and stop time for each jobs, Total minutes spent

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    33 bids

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

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    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    $20 / hr (Avg Bid)
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    9 bids

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

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    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

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    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

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    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

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    27 bids

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be ...individual modules are successfully executing but the final result doesn't appear which you can help me in debugging the same ) Note: Problem in debugging the code Language used : VHDL

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    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

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    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

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    20 bids

    build a communication block in VHDL at Xilinx environment

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    Implement Communication VHDL Comm port on Xilinx FPGA part

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    i have a task related to Communication VHDL Xilinx, i will share the details in chat.

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    FPGA TCPIP implementation using Verilog

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    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

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    i need vhdl project for fpga bord i need skeleton and can move

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    14 bids

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

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    21 bids

    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

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    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

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    I need some help with selling something. I need a person to sell Afghan white marble on commission basis $200 Per deal will be offered if the deal converts into sales. Minimum required sale should be 1000 Sq.Ft. & in case the Sale is below 1000 [login to view URL] the commission offered will be $100 If the deal converts.

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    Hi mmzkhan, I noticed your profile and would like to offer you an Afghan Calendar design. You can visit our website as below. [login to view URL]

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    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

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    Looking for an Afghan or northwestern Pakistani to translate 10 simple chops printed in Pushtu language into English. This job won't take you 30 minutes. Budget 5 us dollars. Local speakers only, Afghan or northwestern Pakistani only, no agencies.

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    I need you to implement a vcdl design project

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    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

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    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

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    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
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