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    4,767 verilog ascii jobs found, pricing in USD

    Hi Alka, I am looking for someone to do an easy but comber...meteorological data, global and I only need the time series of two points, an ensemble, the data consists of an ensemble of 30 runs and from each I just need those 2 points in ascii or some other easy to access format. I think it should not take more than 5 hours but it will depend of course

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    Interface between MCU / SDR for conversion of raw data to ASCII format and posting to http post. Polling algorithm with sending and ACK protocols

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    assembly emu8086 3 days left

    ...that contains ASCII encoded text. Then the program will process the file to count the number and type of characters in it, and then display on the screen the statistics counted from the file. The program should count the following different types of characters each on its own: 1- All small letter ASCII characters. 2- All large letter ASCII characters

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    Required a small class file .net 4.5 c# to convert a .jpg file or font file to a structured ascii data and produce a zpl string to send to a printer. Documentation for the requirements on the converted files and the zpl commands are in the attached file. Class must accept a file location for the file to be converted, file location for on the printer

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    Need a serial multiplier coded in system verilog

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    I have a serial adder that I need converted to serial multiplier in system Verilog. very easy only 1 hour work

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    i need a code for serial multiplier using verilog not from online please

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    Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...

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    For a security application, a Flash-Storage SST26VF016B was desoldered from a printed circuit board and ad...content over the UART Interface in HEX. Also need to develop an additional routine where the content of each register will only be displayed if the read byte is a readable (ASCII) character (0-9 and a-Z), discard the other unreadable bytes.

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    ...lidar data must be read and converted to ASCII file using the manuel of lidar. Firstly, the software will reach the packets in the pcap. Secondly, the packets must converted to values ( time, azimuth, lase ID etc.) with respect to the Velodyne Manuel. As a result, after processing a pcap file, I have to get a ASCII file contains the values of measurements

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    i need a verilog code for serial multipler

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    Need help cleaning up some code, and matrix multiplication.

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    hi, looking for an IoS app development - with 3 to4 GUI screen , provision for the user to key in ascii values and send the data over Wi-Fi interface to open Access point unit in sight also read back from the Access point and display.

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    need a neural network that can identify brain signals into ASCII text. My hardware is epoc emotiv and i have the emokit working with it on linux.

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    I need Verilog Code for BMI calculation that can be running in Quartus software.

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    I want someone to make a 40 minutes video to teach me how to Use cadence tool to synthesize digital circuit from Verilog code and simulation and do the static timing analysis and static power analysis in a given digital circuit which contains XORs and Multiplexers

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    ...parity No flow control 115.2k baud The local host is accessing the pi using serial code written in php is done. Raspberry pi send data from local host in form of ASCII characters to the terminal (like teraterm and hyperterm) and get response back at local host-- Done We have already set all specifications for Mini com and terminal communication

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    We require a simple oscilloscope project to be implemented using only Verilog code on DE1-SoC board by the latest date of 7th of May as agreed during the chat conversation. This project will comprise of modular Verilog code, fully commented, test-benches for verification and a technical report of the project. Altera Quartus software will be used for

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    We require a small program to be written that converts file ...require a small program to be written that converts file formats between two ASCII formatted files. The files are basically a list of co-ordinates that are used for a flight plan for a UAV, and we require the co-ordinates to be read and written out in two different ascii formats.

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    A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.

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    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

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    ...to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not quite sure with the Verilog language

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    ...hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience

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    Verilog code of Simplified DES algorithm

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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

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    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think t...any other sensors I haven't mentioned will work better? Therefore, I think we need some chat to find a solution before start working. FPGA: Xilinx Basys3 Language: Verilog HDL Software: Vivado 2015.4

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    ...PHP Socket programming send and receive Data project. Description: - I have a dedicated php server hosted on cloud (GoDaddy) - I have an external modem which can send ascii data string on this server's ip on a specific port. - I need a program to capture the data stream on using sockets to capture data on specific tcp port and capture the data

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    ...YOU able to integrate merchant accounts with shopping cart? i will receive the data in the following formats. • Comma delimited • Pipe delimited | • Tab delimited Ascii Char 9 are you able to work with that? at present the site is is built on a template, will you format it to what i need to sell including categories etc? Also i will need

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    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

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    ...returns a list where all uppercase letters have been converted to lowercase letters. Hint: The ML functions ord and chr could be useful here, as would the knowledge of the ASCII values for A and a. The function call changeToLowercase [#”a”, #”A”] should return [#”a”, #”a”] d. getLast: given a list, this function returns the last i...

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    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

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    200418_Verilog Ended
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    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

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    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

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    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

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    Tcp sending on FPGA using verilog xgmii xilinx vivado

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    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

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    more details will be given in the chat

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    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

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    PALINDROME! Ended
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    ...returns a list where all uppercase letters have been converted to lowercase letters. Hint: The ML functions ord and chr could be useful here, as would the knowledge of the ASCII values for A and a. The function call changeToLowercase [#”a”, #”A”] should return [#”a”, #”a”] d. getLast: given a list, this function returns the last i...

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    the program is written using PLP 5.2 You program will receive ASCII strings from the UART, one character at a time. It should convert each string of characters into an integer value that is passed to a provided print function. Strings will be terminated using a semicolon (;) character and will contain one or more characters in addition to the semicolon

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    ASCII text file format. Windows 7. Single seat operation on single desktop computer. Use browser to locate subject file. *.txt extension type is default. On screen provide a user button to initiate automated file examination process. Individually examine each line within subject file. If numeric data is populated within cells 151 -159 only insert

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    ...GIS data files. There will be Track lines including colours Marker positions including symbol and colours Depth points I would like this converting into ascii text so it is readable by other systems i have information on an earlier file format but the method seems to have changed in this version. i can also provide the

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    Hello. I have an 80,000 line ASCII text file (XYZ) for a geology resource voxel shape. I need someone please to convert this raw format to a higher-level voxel format such as Vulcan, Geosoft, MapInfo Discover 3D etc. It then needs to be exported as 3D DXF/DWG, then given an overall isosurface and again exported as DXF/DWG. Required immediately.

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    Small project on computer architecture

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    I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated

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    I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools)

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