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    4,887 verilog ascii jobs found, pricing in USD

    I want to implement the Ethernet connection. The deliverables are as follows -Verilog code to run on a Spartan 6 Board - (xc6slx100) -simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 1000mbs.

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    Simple project, that basically should detail the observed waveforms and max frequency of given code.

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    Hi Behailu D., I noticed your profile and would like to offer you my project. We can discuss any details over chat. conversion python to verilog

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    i need to convert a python code into verilod hdl.

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    Verilog code 1 day left

    Please do what is in the paper and hand me the code, testing waveforms and synthesized diagrams

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    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

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    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

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    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

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    Code needs to be ported from Matlab to Verilog

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    ...the control socket, the most important camera and image settings as well as the mode of the program can be changed via simple ASCII functions. In general, this is a simple mapping of 20 different functions of the library for ASCII remote control by scripts. - Image data should be transferred via the data socket or saved to files, depending on a selected

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    ...to a file on local phone storage and specified cloud drive (if outputting mesh, separate points from faces in output so that points are not repeated). May use a standard ASCII 3D geometry format if desired Point cloud should be expressed in Euclidean space with Cartesian or spherical coordinates If possible, point cloud should be expressed to actual

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    I need to recreate a console based version of Space Invaders using C++/C#. I don't really care about graphics, may be ASCII-like. Here are the requirements: 1. "Aliens" don't have to move, they should shoot from time to time. 2. Game should be played by computer, something like bot. It should automatically move left/right to avoid being shot and shoot

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    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

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    Open file dialog for source file Destination file is same but extension .dxf is appended Read (xc, yc, W, L, theta) data from an ascii file (xc, yc) are rectangle center in mm (W, L) are width and length in mm theta is CCW rotation in degrees e.g. this draws "S4" in crude rectangle font. -0.187883 0.071279 0.001500 0.010605 45.000000 -0.180383

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    I need someone with Cadence Allegro to export an allegro PCB layout into ascii (.ALG) in order to import it in Altium.

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    Hello, in site I am running script in ASCII, the site build in Opencart. the task is to define the text we are getting from users: Full name, address, city and comment: Need to define fix place so it will with same place in all files after order made. for each section should be 25 characters and 10 characters space between each one, now it too much

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    ...with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the

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    1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

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    Hi All, We are looking for the Developer who can help us to Interface Pathology Laboratory Instrument using Serial RS 232 and TCP IP ( ASTM & HL-7 ). Devel...can help us to Interface Pathology Laboratory Instrument using Serial RS 232 and TCP IP ( ASTM & HL-7 ). Developer should have knowledge of Transmission Protocol / Layers. ASCII /HEX Codes

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    ...'Note off', 'Note on', 'Note off'. In a custom Processing script, I stripped away these unnecessary characters, and converted the 88 pitches of the piano into 88 different ASCII characters. To allow for multiple notes to be played at the same time, I entered in spaces, to show where each unit of time ticks by." I need it to be able to go both ways

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    Hi, I need some simple functions written in python (with NO external modules) that will help me do ASCII Art. For Example I need a function that will draw a triangle like: x xx xxx xxxxx xxxxxx, and will take as parameters number of lines that I want to generate and how many spaces should be put before first top X. So I can do a christmas

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    ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG

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    I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting EDA tools usage

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    Need someone who has the tools and/or ability to convert a relatively simple verilog (.v) file to liberty timing (.lib) format, and who can verify the resulting .lib file. If successful and painless, there will be more such projects.

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    It is required to implement the lyra2z cryptographic algorithm on the FPGA. Series FPGA Ultrascale Kintex language Verilog. [login to view URL]

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    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    Hey, I have a project that needs to be done in Verilog and Vivado and I'll share details to anyone interested.

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    Just need to design the Snake Gane as per my specifications. I am using Nexys 4 development board.

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    This is a project in extension to an open source github pro...we control. Deliverables are: (1) a simple webpage with cookies taht contain a stort string of ASCII-based characters (2) python code to get the loaction of the cookies for a current version of IE, Edge, Firefox and Chrome and (3) python code to read ASCII content (string) from the cookies.

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    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

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    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

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    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

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    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

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    I have a small piece of code that reads in an ASCII Autocad dxf file. This needs to be read into an array of structs where the struct is an Int and a String. For small files the way this is implemented is fine. But for large files, ~12.4 GB, it grinds to a halt taking about half an hour as the amount of memory required explodes to ~75 GB. Looking for

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    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

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    ...STM32F103 and STP16CPC26XTR (16 channels led driver controller) The software can receive information via RS485 (serial port) and CAN BUS. You can receive 5 frames: Left Text (5 ASCII char) (5 bytes) Right Text (5 ASCIIchar) (5 bytes) State of linear bar, state of curved bar and state of arrows and central LEDs (2 Bytes) Brightness level (1 Byte). General

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    I have project ready already just need some help!

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    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

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    We manufacture hardw...program will need to be able to identify local ports (on PC or PI), choose communications settings and open ports for communications. We need to be able to send commands (in ASCII) and receive responses through buffers that we can further process or store. We'd like to have a common code base (PC and PI) that we can build upon.

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    I have 9 pairs of characters let's say 1g 3d 5f zz 90 00 00 3e 11 I need to do the...designated cell but if it was 2d instead to type jhon instead of Mark. 3. If the 2nd pair is 59 to type "carpenter" 4. If the 4th pair is 7h then Type the equivlant value in Ascii. Doing it in Visual Basic is possible as well. I need the source code as well please.

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    I am looking a basic PHP script to connect a cricket bowling machine on serial port and operate via PHP script. I provide all ASCII based commands.

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    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

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    I need a libreoffice-writer extension/addon that, based on the number provided in a.x.y.z format builds me a frame, inside which a non-ascii set of characters are inserted and displayed in the middle of editing a libreoffice writer document. These utf-8 strings would be pulled from a dictionary (or a database) uploaded by the coder, in the given extension

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    we need a technical content writer who knows the system Verilog, OVM and UVM.

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    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

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    (1)Key generation. (2...a sentence, convert it to ASCII codes, divide it into blocks, encrypt each block with the round keys, and output the ciphertext of the sentence. (iii)For decryption, input the ciphertext (cut/paste), divide it into blocks, decrypt each block with the round keys, convert the plaintext to the sentence on the basis of ASCII codes

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    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

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    Please refer the att...the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

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    We need to fix a program VS2008 program so it will generate an ascii (XML) file the right way. See attachment. Look at [login to view URL] to see how the result should look like after your fix. Need an experience Visual Studio C++ programmer. SQL knowledge

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