Verilog code jobs

Filter

My recent searches
Filter by:
Budget
to
to
to
Skills
Languages
    Job State
    1,356 verilog code jobs found, pricing in USD
    FPGA TCPIP implementation 5 days left
    VERIFIED

    FPGA TCPIP implementation using Verilog

    $21 / hr (Avg Bid)
    $21 / hr Avg Bid
    12 bids

    Verilog digital logic deisgn simple work

    $23 (Avg Bid)
    $23 Avg Bid
    18 bids

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    $46 (Avg Bid)
    $46 Avg Bid
    16 bids

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    $23 (Avg Bid)
    $23 Avg Bid
    22 bids

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    $22 (Avg Bid)
    $22 Avg Bid
    17 bids

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
    $21 / hr Avg Bid
    20 bids

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
    $131 Avg Bid
    19 bids

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
    $122 Avg Bid
    13 bids

    We are looking for a System Verilog Training for few Engineers in our premises.

    $1983 (Avg Bid)
    $1983 Avg Bid
    5 bids

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
    $100 Avg Bid
    8 bids

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $123 (Avg Bid)
    $123 Avg Bid
    20 bids

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
    $184 Avg Bid
    15 bids

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
    $86 Avg Bid
    5 bids

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $106 (Avg Bid)
    $106 Avg Bid
    11 bids

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $132 (Avg Bid)
    $132 Avg Bid
    7 bids

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [login to view URL] Using PG236 [login to view URL]

    $128 (Avg Bid)
    $128 Avg Bid
    3 bids

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    $72 (Avg Bid)
    $72 Avg Bid
    1 bids

    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    $42 / hr (Avg Bid)
    $42 / hr Avg Bid
    1 bids

    I need image encryption using verilog on FPGA board

    $803 (Avg Bid)
    $803 Avg Bid
    13 bids

    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

    $29 (Avg Bid)
    $29 Avg Bid
    16 bids

    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    $563 (Avg Bid)
    $563 Avg Bid
    11 bids
    $80 Avg Bid
    1 bids

    Hi, I want a 2D convolution module in Verilog, using DSPs.

    $45 (Avg Bid)
    $45 Avg Bid
    8 bids
    Quartus Ended

    I need you to develop some software for me. I would like this software to be developed for Linux . Edit the code in FPGA Board of a printer written in Verilog language.

    $27 (Avg Bid)
    $27 Avg Bid
    2 bids

    I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

    $106 (Avg Bid)
    $106 Avg Bid
    10 bids
    $125 Avg Bid
    3 bids

    I have a serial adder that I need converted to serial multiplier in system Verilog. very easy only 1 hour work

    $20 (Avg Bid)
    $20 Avg Bid
    6 bids

    i need a code for serial multiplier using verilog not from online please

    $42 (Avg Bid)
    $42 Avg Bid
    12 bids

    Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...

    $108 (Avg Bid)
    $108 Avg Bid
    10 bids

    i need a verilog code for serial multipler

    $31 (Avg Bid)
    $31 Avg Bid
    8 bids

    Need help cleaning up some code, and matrix multiplication.

    $50 (Avg Bid)
    $50 Avg Bid
    7 bids

    I need Verilog Code for BMI calculation that can be running in Quartus software.

    $141 (Avg Bid)
    $141 Avg Bid
    2 bids

    I want someone to make a 40 minutes video to teach me how to Use cadence tool to synthesize digital circuit from Verilog code and simulation and do the static timing analysis and static power analysis in a given digital circuit which contains XORs and Multiplexers

    $38 (Avg Bid)
    $38 Avg Bid
    5 bids

    We require a simple oscilloscope project to be implemented using only Verilog code on DE1-SoC board by the latest date of 7th of May as agreed during the chat conversation. This project will comprise of modular Verilog code, fully commented, test-benches for verification and a technical report of the project. Altera Quartus software will be used for

    $210 (Avg Bid)
    $210 Avg Bid
    1 bids

    A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.

    $226 (Avg Bid)
    $226 Avg Bid
    12 bids
    $80 Avg Bid
    1 bids

    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

    $78 (Avg Bid)
    $78 Avg Bid
    1 bids
    $23 Avg Bid
    1 bids

    ...to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not quite sure with the Verilog language

    $127 (Avg Bid)
    $127 Avg Bid
    11 bids

    ...hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience

    $347 (Avg Bid)
    $347 Avg Bid
    3 bids

    Verilog code of Simplified DES algorithm

    $24 (Avg Bid)
    $24 Avg Bid
    9 bids

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $283 (Avg Bid)
    $283 Avg Bid
    11 bids

    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think t...any other sensors I haven't mentioned will work better? Therefore, I think we need some chat to find a solution before start working. FPGA: Xilinx Basys3 Language: Verilog HDL Software: Vivado 2015.4

    $182 (Avg Bid)
    $182 Avg Bid
    6 bids

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    $158 (Avg Bid)
    $158 Avg Bid
    16 bids

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    $122 (Avg Bid)
    $122 Avg Bid
    10 bids
    200418_Verilog Ended
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    $50 - $80
    Sealed
    $50 - $80
    4 bids

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    $388 (Avg Bid)
    $388 Avg Bid
    6 bids

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    $29 (Avg Bid)
    $29 Avg Bid
    11 bids

    Tcp sending on FPGA using verilog xgmii xilinx vivado

    $409 (Avg Bid)
    $409 Avg Bid
    4 bids

    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

    $416 (Avg Bid)
    $416 Avg Bid
    5 bids