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1,189 verilog freelance jobs found, pricing in USD

(vinodluhar's) 10G sfp+ port will be read , using xilinx's free IPs , udp data will be filtered out, based on udp data content, and will be passed to other ethernet port, memory and ACP port of Zynq, using AXI interface with test bench for simulation.

$1194 (Avg Bid)
$1194 Avg Bid
9 bids

(vinodluhar's) 10G sfp+ port will be read , using xilinx's free IPs , udp data will be filtered out, based on udp data content, and will be passed to other ethernet port, memory and ACP port of Zynq, using AXI interface with test bench for simulation.

$1250 (Avg Bid)
$1250 Avg Bid
1 bids

I need help in a verilog question. I am a beginner in verilog so need some help.

$19 (Avg Bid)
$19 Avg Bid
16 bids

I need a small verilog code as soon as possible.

$271 (Avg Bid)
$271 Avg Bid
28 bids

Training using Verilog Altera-Quartus

$55 (Avg Bid)
$55 Avg Bid
1 bids

Training using skype and screen sharing.

$120 (Avg Bid)
$120 Avg Bid
3 bids

I need a small verilog code as soon as possible.

$222 (Avg Bid)
$222 Avg Bid
21 bids
Asic Design / FPGA Ended
VERIFIED

I need someone expert in ASIC design to design digital clock with VERILOG CODE by Quartus software Contact me for more details

$140 (Avg Bid)
$140 Avg Bid
16 bids

design digital clock with alarm with Verilog code / FPGA

$187 (Avg Bid)
$187 Avg Bid
22 bids

required and experienced electronics system designer to draw architecture and implementation of a bridge circuit in verilog for implementation in FPGA. need the work to be done as soon as possible

$185 (Avg Bid)
$185 Avg Bid
10 bids

Implementation of Image processing algorithms on FPGA/CPLD hardware using VHDL, and Verilog, MATLAB

$1864 (Avg Bid)
$1864 Avg Bid
6 bids

...Using Verilog Using Altera (Cyclone V SoC) Interface with Avalon Bus (maybe master) Write to DDR3 Simple C/C++ code to access the data from linux or like Bare metal code. something to do with DDR3 storage from avalon Bus Requirements: BCLK runs 16MHz1 left and right channel is 16 bits sample each side I have Started the Verilog code, or

$69 (Avg Bid)
$69 Avg Bid
3 bids

I have a design in verilog. I need a systemverilog code for verification of the design

$128 (Avg Bid)
$128 Avg Bid
14 bids

ASIC implementation of SD card controller using Verilog

$161 (Avg Bid)
$161 Avg Bid
9 bids

Game implementado no FPGA

$176 (Avg Bid)
$176 Avg Bid
8 bids

I am looking for a freelancer to help me with my project. The skills required are FPGA, Software Architecture, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

$414 (Avg Bid)
$414 Avg Bid
32 bids

Implementar um jogo em verilog ou vhdl em vga

$143 (Avg Bid)
$143 Avg Bid
6 bids

Jogo VGA em Verilog para FPGA

$153 (Avg Bid)
$153 Avg Bid
4 bids

Implement algorithms in Xilinx FPGA writing Verilog / VHDL code to generate optimize RTL and create software to test and characterize the algorithms.

$2493 (Avg Bid)
$2493 Avg Bid
12 bids

I want to implement a 2-D FFT on an Xilinx FPGA board Artix 7 chip, it will be used for Radar signal processing.

$208 (Avg Bid)
$208 Avg Bid
18 bids