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    1,310 verilog programming jobs found, pricing in USD

    I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details

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    Hi This...processor for face recognition. i this project i wrote verilog hdl coding and completed Ai algorithm for face recognition. so the next steps is to do the cross compilation of h.264 verilog coding with AI Algorithm. so iam expecting that to complete cross compilisation of h.264 verilog code with Ai algorithm. regards

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    Verilog Testbench for UART 5 days left

    I have designed a UART which works fine and I need a testbench to verify it works perfectly.

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    ...BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Pune. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience

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    -This must be done on System Verilog NOT Verilog. -Need to be able to input random data and have results. -Need Explanation for every step taken and code written. (reason why you used the code and math -behind it) -Must have everything Required in the attachment. -Must be able to explain to someone with zero understanding of the topic This

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    Parameterizable Verilog module that is calculating sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array system.

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    I need someone expert in ASIC design to design digital clock with VERILOG CODE by Quartus software contact me for more details

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    Verilog modify processor design to add pipeline, based on MIPS processor. Existing verilog code provided and more details to be provided.

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    A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .

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    We are developing FPGA using Amazon AWS F1 service. The source code was converted from systemc to verilog using Vivado HLS. Many FPGA tool related issues needs to have an expert to help us. Including: 1) FPGA timing closure constraint 2) Place & route issues. 3) Set up clock divider to CL logic. Potentially, we have a lot more work if you

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    A stepper motor controller in verilog ,

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    A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .

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    I need a Stepper motor controller code in verilog, the controller should take Frequency, direction and number of steps as an input and generate a S shape signal for Driver IC , based on that signal the driver IC will control the stepper motor .

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    ...Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document...

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    autoamate a door handle using vhdl or verilog

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    I have some existing code but need to add a serial connection to the hardware. More details to be provided.

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    Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private

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    I need help completing a Single Cycle RISC-V datapath and control using System Verilog. What I need: - A report including how different instructions have be to implemented. The document contains all the necessary modifications in the datapath to add all the instructions. - Modify the code to implement all the instructions.

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    I'm looking for someone who can write me a verilog HDL code for a servo controller

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    The project details are in the files: [url removed, login to view] or [url removed, login to view] Same file different format.

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