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    1,194 verilog projects done jobs found, pricing in USD

    Pv fed led lighting system: Harmony search algorithm based controller design I am using altium nano board . i need verilog code for above algorithm.

    $130 (Avg Bid)
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    4 bids

    ...application to generate the verilog file(.v) for XGMII 32 bit data and control path using pcap files. The first 8 byte of the first Ethernet frame in the pcap will be used for verilog generation. 1. I will give the pcap file , you will just take the first 8 bytes( 64 bits) of the pcap 2. Programmer will write the verilog to send the data to XGMII

    $60 (Avg Bid)
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    1 bids

    ...the USRP1, including the source files for the FPGA code and corresponding c library. We have working FGPA code for a 2 TX and 2 RX system, and but need about 15 lines of verilog code ported from the 1 TX and 1 RX system to the 2 TX and 2 RX system. Also, we need the working c libary in the transceiver (1 Tx and 1 RX) modified to support the 2 TX and

    $1196 (Avg Bid)
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    16 bids

    i am looking for the VHDL or Verilog code that have UDP or TCP protocol and can have Lan connection fpga spartan 6 to pc by wiznet W 5300 . anyone can help me for that?

    $101 (Avg Bid)
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    Hi, The vision I have in mind is comparable to a machine vision camera. CMOSIS CMV2000/4000 cmos sensor will be readout over LVDS channels and acquired data compressed with H264 encoder (MPEG 4) and compressed data will be send over GigE and/or USB 3.0. I'm a PCB designer with RF design experience, for this project: 1. Propose design architecture ( Pure FPGA, FPGA+controller, DSP or SoC ...

    $2902 (Avg Bid)
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    6 bids

    (vinodluhar's) 10G sfp+ port will be read , using xilinx's free IPs , udp data will be filtered out, based on udp data content, and will be passed to other ethernet port, memory and ACP port of Zynq, using AXI interface with test bench for simulation.

    $1194 (Avg Bid)
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    9 bids

    (vinodluhar's) 10G sfp+ port will be read , using xilinx's free IPs , udp data will be filtered out, based on udp data content, and will be passed to other ethernet port, memory and ACP port of Zynq, using AXI interface with test bench for simulation.

    $1250 (Avg Bid)
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    1 bids

    I need help in a verilog question. I am a beginner in verilog so need some help.

    $19 (Avg Bid)
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    16 bids

    I need a small verilog code as soon as possible.

    $271 (Avg Bid)
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    28 bids

    Training using Verilog Altera-Quartus

    $55 (Avg Bid)
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    1 bids

    Training using skype and screen sharing.

    $120 (Avg Bid)
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    3 bids

    I need a small verilog code as soon as possible.

    $222 (Avg Bid)
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    21 bids
    Asic Design / FPGA Ended
    VERIFIED

    I need someone expert in ASIC design to design digital clock with VERILOG CODE by Quartus software Contact me for more details

    $140 (Avg Bid)
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    16 bids

    design digital clock with alarm with Verilog code / FPGA

    $187 (Avg Bid)
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    22 bids

    required and experienced electronics system designer to draw architecture and implementation of a bridge circuit in verilog for implementation in FPGA. need the work to be done as soon as possible

    $185 (Avg Bid)
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    10 bids

    Implementation of Image processing algorithms on FPGA/CPLD hardware using VHDL, and Verilog, MATLAB

    $1864 (Avg Bid)
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    ...Using Verilog Using Altera (Cyclone V SoC) Interface with Avalon Bus (maybe master) Write to DDR3 Simple C/C++ code to access the data from linux or like Bare metal code. something to do with DDR3 storage from avalon Bus Requirements: BCLK runs 16MHz1 left and right channel is 16 bits sample each side I have Started the Verilog code, or

    $69 (Avg Bid)
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    3 bids

    I have a design in verilog. I need a systemverilog code for verification of the design

    $128 (Avg Bid)
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    14 bids

    ASIC implementation of SD card controller using Verilog

    $161 (Avg Bid)
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    9 bids

    Game implementado no FPGA

    $176 (Avg Bid)
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    8 bids