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    1,231 verilog projects jobs found, pricing in USD

    Jogo VGA em Verilog para FPGA

    $163 (Avg Bid)
    $163 Avg Bid
    3 bids

    Implement algorithms in Xilinx FPGA writing Verilog / VHDL code to generate optimize RTL and create software to test and characterize the algorithms.

    $2538 (Avg Bid)
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    11 bids

    I want to implement a 2-D FFT on an Xilinx FPGA board Artix 7 chip, it will be used for Radar signal processing.

    $208 (Avg Bid)
    $208 Avg Bid
    18 bids

    I am looking for a freelancer to help me with my project. The skill required is Verilog. I need to complete the project by 6/23/2017. Project is to write verilog code for digital alarm clock. I have most of the code. Need help with two modules.

    $130 (Avg Bid)
    $130 Avg Bid
    19 bids

    ...not return a ack. So to keep bench happy * For PIO_wr ack should be returned immediately. For PIO_rd wait for data back and then send ack Please create such a system verilog UVM bench ? I need it pretty quick. Once i have this I can discuss more on this. Note: The agent sequences should generate sequences using uvm_create(req), start_item(req)

    $91 (Avg Bid)
    $91 Avg Bid
    4 bids

    I am looking for a freelancer to help me with my project. The skill required is Verilog. I need to complete the project by 6/23/2017. Project is to write verilog code for digital alarm clock. I have most of the code. Need help with two modules.

    $25 (Avg Bid)
    $25 Avg Bid
    2 bids

    I am looking for a freelancer to help me with my project. The skills required are Matlab and Mathematica, Software Architecture, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.

    $138 (Avg Bid)
    $138 Avg Bid
    16 bids
    matlab Ended

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.

    $16 (Avg Bid)
    $16 Avg Bid
    3 bids

    I am looking for a freelancer to help me with my project. The skills required are FPGA, Software Architecture, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files. and also i am searching for phd project if you have

    $365 (Avg Bid)
    $365 Avg Bid
    20 bids

    I am looking for a system verilog trainer for a client. The training is in chennai for a minimum of three days. The training should begin with fundamental and train upto to advanced level 4.

    $155 (Avg Bid)
    $155 Avg Bid
    9 bids

    Segue trabalho em anexo

    $150 (Avg Bid)
    $150 Avg Bid
    10 bids

    Need Embedded Designer Who has Excellent skills in ARM/AVR C/C+, Embedded c programing for designing a hardware module for an agricultural product. Verilog and VHDL are Added Advantage

    $466 (Avg Bid)
    $466 Avg Bid
    18 bids

    Hi seshupower, I am an experienced professional in verilog/VHDL design and working on spartan FPGA board since past 10 months. Kindly let me know if you have any freelancing work for me. Thank you

    $20 / hr (Avg Bid)
    $20 / hr Avg Bid
    1 bids
    fpga Ended

    I am looking for a f...looking for a freelancer to help me with my project. The skills required are FPGA, DSP, Software defined Radio , RF MODEM, Matlab , Communication, Waveform generate, , and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

    $647 (Avg Bid)
    $647 Avg Bid
    33 bids

    You will implement a subset of the pipelined MIPS architecture in system verilog. You will implement a functioning outline of the pipelined processor for a small set of instructions, including: decoding all the instructions you will encounter in this project, implementing most of the MIPS pipeline, correct implementation of arithmetic and

    $2388 (Avg Bid)
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    2 bids

    VHDL/ Verilog code development for Spartan 6 Slx9 to control SPWM using ADC interface along with training for code uploading on board and testing

    $148 (Avg Bid)
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    13 bids
    matlab Ended

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is R$750 - R$2250 BRL. I have not provided a detailed description and have not uploaded any files.

    $234 - $701
    $234 - $701
    0 bids

    I need a 16 bits floating point multiplier, with one pipeline level. I dont need a very complex circuit.. One as easy as it can be would be perfect. I would like a short description of the blocks too. I attached a flow graph for the multiplier.

    $43 (Avg Bid)
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    3 bids

    I need help with verilog/ vhdl project. Please bid here if you can do it. Thanks a lot.

    $38 (Avg Bid)
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    33 bids

    ...have [url removed, login to view] in Sim folder. It tests every single instruction. It even tests some instructions under a few different conditions. After you run this program on your Verilog design, you should make sure that you see the "after =" values in the marked memory locations. Other locations do not change. A few locations may

    $55 (Avg Bid)
    $55 Avg Bid
    8 bids