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    1,330 verilog projects jobs found, pricing in USD

    Code for a specific signal passing through some noise being received on the other side. Complete with testbench

    $161 (Avg Bid)
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    17 bids

    looking for someone who can write a code to parse below code(using pyparsing) immediately : module module-name(input a, input b, input c, output r); wire mid1; mid1=a&(~b) wire mid2=b|c; wire mid3=a|c,mid4=b&c; wire mid5,mid6; mid5=a|(~c); mid6=a&b; r=mid5|mid6 endmodule *we have 4 ways to define wire as shown in above example *each (input, output, module, wir...

    $20 (Avg Bid)
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    3 bids

    Contact me for more details. All I need done is porting some VHDL to Verilog.

    $118 (Avg Bid)
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    18 bids

    ...this. "If SystemVerilog is so good, why do we need the UVM? ". The article needs to start by answering this question in title. The target audience will be experts in System-Verilog and knows concepts of UVM. The article needed to be original and meaningful content. Please bid with your experience in UVM so that I can provide the project to you quickly

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    I need help in my company project (more details will be share with shortlisted candidate) You have to be very good in MIPS assembly language RTL, verilog, and basics VLSI technology to be shortlist you have to solve one MIPS Asm. question (attached below) as soon as possible.

    $971 (Avg Bid)
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    In my project , I have to generate gps signal using verilog code. For this I need C/A code, random data, carrier signal. So first I have to do bpsk to random data and c/a code then do bpsk with carrier signal . I have given you c/a code you have generate random data , carrier signal and give me output code as well as pictures within 1 or 2 days.

    $34 (Avg Bid)
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    Hii. I want someone can write verilog language and this vedio [url removed, login to view] have 10 mode ,,I want 5 mode of the same video ,,my blackpord is "DE1 ALTERA".

    $39 (Avg Bid)
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    Write a simple verilog code to create dynamic lighting using led. see the attached files and respond

    $125 (Avg Bid)
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    24 bids

    It is to Implement a 16-bit CORDIC Computer. The design to be implemented is based on a bit-serial configuration. It will take ...signed binary fixed point number, corresponding to an angle in the range 0 to π/2, and use the CORDIC method to find the sine and cosine of this angle. This will be coded in Verilog and implemented on the Basis 3 board.

    $152 (Avg Bid)
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    im making missile command and i have (x1,y1) and (x2,y2). how can I calculate the x step and y step values?

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    I have .vhdl files for an implementation of google chrome's 'dino run' which appears when the user has no wifi connection. However, I would like to...vhdl files for an implementation of google chrome's 'dino run' which appears when the user has no wifi connection. However, I would like to have the same functionality with Verilog description language.

    $124 (Avg Bid)
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    Plz contact me. I have other code for it as well. You will just need to restructure the code and it should be good enough.

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    does anyone experienced with verilog have de2-115 I need help displaying a sprite on the screen. I have all the files.

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    윈도우 기타 또는 불분명 3x3 Systolic array matrix using ram and rom

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    2 bids

    i need someone who can do putty and verilog

    $142 (Avg Bid)
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    MATLAB code a bit-serial CORDIC computer in Verilog to compute the sine and cosine of an angle θ. I will share the additional details later

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    15 bids

    the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project

    $83 (Avg Bid)
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    Hi Chaudhry Talha H., I noticed your profile and I am interested in hiring you for a Verilog Design Project. Maybe we could discuss the details properly over the chat.

    $11 / hr (Avg Bid)
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    Hi Buzdugan A., I noticed your profile and I am interested in hiring you for a Verilog Design Project. Maybe we could discuss the details properly over the chat.

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    there are two short python project and verilog project all of them are really too short it will not take time, you can it in the rar file, 1 and 2 for python 3 for verilog

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    6 bids