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    2,700 verilog vhdl jobs found, pricing in USD
    VHDL coding 3 days left

    HDL coding from block diagram and pseudo algorithm

    $25 (Avg Bid)
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    5 bids

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $178 (Avg Bid)
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    17 bids

    Develop a musical bell that will play a selected and programmed song in the FPGA.

    $86 (Avg Bid)
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    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

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    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $110 (Avg Bid)
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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow)...implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

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    VHDL expert needed 4h left
    VERIFIED

    Expert in VHDL needed to work on a code

    $13 / hr (Avg Bid)
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    16 bids

    Small project to write in VHDL

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    24 bids

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [login to view URL] Using PG236 [login to view URL]

    $128 (Avg Bid)
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    3 bids

    Implement an algorithm in vhdl done in Matlab using System Generator

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    ...5ms / 20ns = 125000 dcycle_mid = (dcycle_max – dcycle_min) / 2 = 75000 Για την περιστροφή του servo θα χρησιμοποιήσουμε τα δύο κουμπιά π&omic...

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    1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events important

    $77 (Avg Bid)
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    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    $75 (Avg Bid)
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    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    $42 / hr (Avg Bid)
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    Necesito hacer un programa en VHDL de un reloj (formato 24hs), con cronometro y con alarma. Cuando cambio a cada uno. no se debe perder la cuenta de la hora, cronometro o la alarma seteada. El reloj, la alarma y el cronometro se debe poder cargar/modificar manualmente. Detención y reinicio del cronometro. Cuando la hora del alarma coincida con el clock

    $180 (Avg Bid)
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    I need image encryption using verilog on FPGA board

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    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

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    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    $563 (Avg Bid)
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    Need to Develop one VHDL Program. more details will be provided on chat.

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    1 bids

    Implement a program on VHDL

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    vhdl code for wireless adhoc network and its implementation in FPGA,

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    Convert C code to VHDL for BDLC, see attached datasheet. C code is available from TI website (or I can provide). Need to convert code, which is based on document into VHDL. Deliverables: VHDL code + working testbench + block diagram Need to be knowledgeable in Motor Control, C/C++ and VHDL.

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    Help with a few questions on VHDL

    $27 / hr (Avg Bid)
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    Hi, I want a 2D convolution module in Verilog, using DSPs.

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    8 bids
    Quartus Ended

    I need you to develop some software for me. I would like this software to be developed for Linux . Edit the code in FPGA Board of a printer written in Verilog language.

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    I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

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    9 bids

    I want someone to write in vhdl an 8-bit harvard architecture CPU

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    BId only if u can do only the second...dropping it and seeing it through a stereoscope lensIn perspective projection and the use of two center projection (off-axis projection) 2,Implement hardware system using vhdl language and xilinx 9.2i software And executed on spartan -3e linen The graphic is displayed on an external screen only the second Part

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    Write a VHDL code to use two ultrasonic sensors as detectors, placed one at entrance and other at exit of a parking space. When the ultrasonic detects a car, use a counter to count the cars entering and decrement when a car exits. There is an RGB led place at each gate (entry &exit) which is used to indicate opening and closing of gates. Entry gate

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    in this project i need just read a analog signal on altera cyclone 5 board and also to realize pt1 element with simple response a(t)=(1-e^-t/T)....it's a simple project and i can explain you in more detail ....so i just want this to signal at the out i.e on gpio pins

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    I have a serial adder that I need converted to serial multiplier in system Verilog. very easy only 1 hour work

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    working with a grideye infrared sensor and looking to send the data through a wifi Cypress connection. We have some experience with this already but i am looking ...this so that we can work back and forth to get this up and running. I would like to send the data to a be read out with a Visual C sharp interface. Experience with FPGA and VHDL is a bonus

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    i need a code for serial multiplier using verilog not from online please

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    I require source code for the design and simulation verification of a calculator (Not + - / * operations) with slightly more experienced VHDL'ers can be selected for this quick project

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    I require a VHDL deisgn code, to construct a simple calculator for two input numbers, testbench and simulation for verification of functionality before using the board.

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    Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...

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    i need a verilog code for serial multipler

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    I need some help with VHDL/FPGAs. I am stuck with some part and would like to fix it asap.

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    Need help cleaning up some code, and matrix multiplication.

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    I have a Spartan 6 lx9 dev board. I would to connect the board to my computer and perform standard arithmetic calculations and will require help setting up the calculator.

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    Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. It embeds the chip ADS5522 too. This is the ADC. I already have a not-completed project written in vhdl including modules parts of this project. I need you to simulate and fix the data transmission part between the client

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    I'm currently a 4th year degree student undergoing a project to build a Multiplexed DDS using iCE40UP5K breakout board. Apart from the Multiplexed DDS core itself, an i2s module for a DAC chip, Encoder modules for control of waveform parameters and an LCD module are present. Functional verification is done and behavior in simulation is as expected. What is needed is proper post-synthesis ...

    $116 - $581
    Featured Urgent Sealed
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    5 bids

    I need some urgent help with VHDL and python for a task which is very important for me!

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    Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. I already have a complete project written in vhdl including other modules apart of this project. I need you to simulate and fix the data transmission part between the client application to the DAC AD9764, which is

    $199 (Avg Bid)
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    8 bids

    need vhdl to run in board equipment with festive lights........................................................................................................................................................embedded systems project

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    I need Verilog Code for BMI calculation that can be running in Quartus software.

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    3 bids

    I want someone to make a 40 minutes video to teach me how to Use cadence tool to synthesize digital circuit from Verilog code and simulation and do the static timing analysis and static power analysis in a given digital circuit which contains XORs and Multiplexers

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