We are looking for an experienced FPGA developer to write technical documentation related to Xilinx and Verilog development as well as custom hardware accelerators. Content is in the form of educational papers for semi-technical audience. Each article/paper is expected to be around 1900 words (4-5 pages, plus custom diagrams/infographics). Candidates
FPGA Sensor Interface Design Other - Engineering & Architecture Posted May 18, 2019 This is a two part project. The first phase consists of the following tasks - 1. Prototype TI LDC1101 and TI ALS31300 sensor interfaces using FPGA dev board, ALS31300 IC & LDC1101 on Schmart boards. Both footprints should be the same, please confirm 2. Prepare configuration
We require an FPGA programmer work with us in the development of 2 module designs for a prototype system. Module 1 will include communication with an image sensor via MIPI CSI2, and writing image data to local memory. Module 2 will have an FPGA that will control multiple MIPI stream processing and other some other functions.
Required USB token based digital signature implementation for document signing on c...time measurement sensor, adding signature word document, flash based digital counter, token based ecommerce, sign signature word document, digital circuit implementation analog fpga, php digital signature html forms, freelancer required find indian based manufacturer
Hi there, This project requires you to develop a high-speed FPGA design for integer division. Only those who have experience in Matlab, SIMULINK, XILINX and SYSTEM GENERATOR the apply. Otherwise please don't. Deadline is Monday. I'll provide the template and algorithm and implementation process. ## Xilinx ISE version 14.4, MATLAB 2012b, Windows 7 or
Hi there, This project requires you to develop a high-speed FPGA design for integer division. Only those who have experience in Matlab, xilinx and system generator the apply. Otherwise please don't. Deadline is Monday and the budget is $50. I'll provide the template and algorithm and implementation process. Xilinx ISE version 14.4, MATLAB 2012b, Windows
I have 2 schemes. One with neuron and with genetic algorithm. I need to combine both to train this neuron via genetic algo. Using VHDL in ISE design suite 14.7. Here is [login to view URL] picture of two symbols that I want to combine(gen - genetic algorithm with build in neuron process, neur4sigm - neuron with sigmoid func). I need to train this neuron with
Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from an electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relationship with the perfect electrical engineering freelancer. Thanks.
Hello, I'm currently working on a project that I am struggling with due to lack of VHDL experience. Want to create an SPI driver and interface it with a Microblaze softcore processor and the on-board accelerometer (ADXL362) so that the processor can read the accelerometer data.
I have some simple VHDL tasks. My deadline is tomorrow. 1. Suggest a structural and behavioral description of a bidirectional cyclic shift register. 2. Suggest a structural and behavioral description of a bidirectional arithmetic shift register. Use parallel generation operators and configuration options. 3. Create a subroutine that performs the conversion
Implementation of FOPID controller based FPGA using VHDL.
I need simple bitstream for Xilinx (Avnet) Ultra 96 FPGA board.
An existing DDR3 controller shall be migrated to the following platforms / DRAMs: - 3 times as existing, but different pinout (in total 4 controllers need to co-exist on 1 FPGA) - 2 times to a 32 bit wide 128Ms deep, dual die (2x16bit) configuration - 1 time to an 8 bit wide 128Ms deep, single die configuration for the first configuration, the write
Project goal is a detailed pin planning and block diagram for a JESD204B data converter application. The following components will be disclosed to applicants: - ADC - FPGA - PLL The interface will work at speeds up to 12.5Gb/s. ADC sample rate will be up to 1Gs/s The deliverables for this project are: - Spreadsheet with pin assignments from FPGA
Design a 4 bit up-down multi-function counter using NEXYS 4 DDR (Artix-7 FPGA) board. The counter should display the count every 10 seconds. The counter will have a reset switch (SW0) or button to initialize the sequence to (0000) when it is 1, direction switch (SW1) to select the counting direction and a counting mode switches (SW2and SW3) to select
Need good FPGA programmer for Ethereum Crypto Mining Need to set up mining rig like this [login to view URL] Tell me in detail your experience in crypto mining and tell me also in detail what specific tasks that you will perform to complete this project
Need good FPGA programmer for Ethereum Crypto Mining Need to set up mining rig like this [login to view URL] Tell me in detail your experience in crypto mining and tell me what you can do to set this miner up for me
Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relation with the perfect electrical engineering freelancer. I need to hire 3 freelancers for 3 copies of the task. Thanks
Project is to create C/C++ software to program Altera FPGA (MAX10) configuration memory from an embedded ARM processor using Altera JAM tools. The target device is MAX10 16M, and embedded CPU is Kinetis. The software must read a JAM file and program the FPGA configuration memory using the JTAG interface, which is bit-banged from the MCU pins. Deliverable
Hi I'm looking for a good vhdl programmer to help me with a code. I'm supposed to bring in a simple logo, then i,m supposed to be able to display the logo on the center of a screen(using a vga connection) and my name on the bottom left corner while being able to flip the logo with a button on my fpga board the deadline is thursday. thank you. I have
We are working on an FPGA based doppler flowmeter with a custom PCB. At the moment, we are in the process of modeling algorithms using raw data recording in Matlab. This freelancer will be tasked with coordinating with the DSP engineer to design and implement changes from the Matlab models into our custom PCB, which Cyclone IV based. There is an existing