Vhdl verilog outsourcing jobs

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    4,609 vhdl verilog outsourcing jobs found, pricing in USD

    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

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    Complete a design that includes most of the elements to be used in the CPU

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    Hello i have a code of piano synthesizer using VHDL (vivado) and i want to understand it and fix it ... can you help me ?

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    Verilog code 5 days left

    Please do what is in the paper and hand me the code, testing waveforms and synthesized diagrams

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    ...ability to extract and critically evaluate data for an unfamiliar digital design problem.‎ • The application of appropriate design methods to the VHDL design.‎ • The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.‎ • Ability to implement your design solution on a commercially available digital Computer

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    Manufacturing business wants to take a daily download excel file from GE Appliance website and create a Macro/VBA tool for non-excel users. The tool would look up our internal part number and box count from a table and output a pick sheet for shipping with customer part number, our part number and number of boxes. Should be able to select time range for lookup and select by GE appliance ship t...

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    I would like an email to send out to new customers which i found online or linkedin. i want to intro myself, tell about company and agenda. this email should bring in leads.

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    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

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    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

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    I am experienced in data entry field... my typing speed is 40 wpm.

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    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

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    Matlab to Verilog 18 hours left

    Code needs to be ported from Matlab to Verilog

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    We are a Dutch Internet Agency offering several services under which SEO. Because we have a lot of work, we are planning to outsource one (and by success multiple) linkbuilding tasks as part of several seo campaigns. Currently the project we want to start to outsource is a [login to view URL] - 9 keywords project each keyword (combination) - > {service name} + {Dutch city} refers to its own la...

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    ...already have this you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the

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    You have to build an address block using VHDL

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    please give me such job that can give me only 150 rs per hour

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    Our business requires outsourcing partners experienced in delivering high quality WordPress websites with our provided themes or your own framework. Please provide your portfolio of work and most cost-effective pricing for a long-term relationship with us!

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    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

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    hello, I have this project where I need to read from files and print the output in one file. I provided a very similar code , that can be modify and Matlab code to generate input files.

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    Hi Hightech Outsourcing BD, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    To stimulate a project-based evaluation approach using VHDL and write a report. More information is contained in the file. Projects need to be written in VHDL and run a simulation for the program using a board. I will need the VHDL code and simulation for the timing diagram.

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    I created this project and fini...created this project and finished the entire code ,but for some reason it is not giving me the correct outputs.I would like help to fix the issue by editing my code. using VHDL in vivado I was able to create successful circular cordic. but when I made my AXI full and run it in SDK, it did not give me the right answer

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    A task compromising of Counter, clock divider, clock enable (CE), and seven-segment display using VHDL and Xinlinx Vivado. Further details will be provided. Deadline 3 days.

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    Project of Description format - PDF links - Video links as discussed earlier.

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    we are a new indian IT company with team of experienced developers in php,wordpress. we need business developer who can outsource projects from outside india. please bid only if you have the ability to outsource projects through various resources. good commission will be provided.

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    ...with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the

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    1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

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    ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG

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    ...ability to extract and critically evaluate data for an unfamiliar digital design problem.  The application of appropriate design methods to the VHDL design.  The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.  Ability to implement your design solution on a commercially available digital Computer Aided

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    am a master student, studying embbeded microelectronic and wireless systems, i need a vhdl code for dual_4_1 multiplexer, for structure, behaviour and dataflow if possiblr. thank you

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    I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting EDA tools usage

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    Need someone who has the tools and/or ability to convert a relatively simple verilog (.v) file to liberty timing (.lib) format, and who can verify the resulting .lib file. If successful and painless, there will be more such projects.

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    ...basis trough 100+ API which is displayed on the website. The entire solution is hosted in AWS. We are looking for an outsourcing service provider (companies only, no individuals) to further develop and maintain the platform. The outsourcing will take place in 3 phases: 1. One month full-time PHP resource to review and fix current code, review and update

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    Requirements: - place of residence - Ukraine; - desirable - experience in setting up and administering CRM-systems for at least 1 year; - Required knowledge of php, mySQL from 1 year; - knowledge level in PHP - Software Engineer, Junior level programmer will not work. Duties: - implementation of CRM projects based on VTiger; - development and implementation of new integr...

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    This is a vhdl and C++ project. requires knowledge of both VHDL and C++

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    It is required to implement the lyra2z cryptographic algorithm on the FPGA. Series FPGA Ultrascale Kintex language Verilog. [login to view URL]

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    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    We are on online company selling a handcrafted product to a niche market in the US and EU. We are looking for an experienced marketer to increase sales and develop converting campaigns on social media, ad-words, and other platforms.

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    Expert on VHDL needed to integrate custome VHDL system in Vivado. He is also expected to create a custome SDK app that can handle this custom peripheral. Please bid if you can do. Due in 36 hours

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    Expert on VHDL needed to integrate custome VHDL system in Vivado. He is also expected to create a custome SDK app that can handle this custom peripheral. Please bid if you can do

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    Hey, I have a project that needs to be done in Verilog and Vivado and I'll share details to anyone interested.

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    I need a new website. I need you to design and build a landing page. Simple landing page that describes a business idea and contact form to collect interest. May progress to include SEO/SEM and building a full fledged website

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    Just need to design the Snake Gane as per my specifications. I am using Nexys 4 development board.

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    A brief about our work : we provide A+ quality projects for companies who outsource projects to us and looking to do the same for any new individual business or companies. We work on almost all possible platforms as well as provide great SERP results for SEO projects and every aspects of digital marketing,App developments(native/hybrid) as well as CRMs. Looking for possible partnership with busin...

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    Hi Hightech Outsourcing BD, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    ...- language : VHDL - IDE : Quartus Prime Lite Edition - Simulations with ModelSim - mini-project : 0) implement a 1680x1050-60Hz mode VGA controller (operating @ 143Hz pixel clock via PLL) 1) store 280x280 8byte/pixel image to on-chip memory (M9k blocks) 2) read image from on-chip memory (using Altera/Intel's RAM-1Port vhdl IP) 3) output

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    i have attached the document below. And i need this on 21st of october.

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    ...have to be ported to VHDL and be integrated before programming the Xilinx V6 FPGA on the transmitter. Complete hardware and many of the software blocks in VHDL are already built by our team. The requirement is urgent. Entire work to be completed in 2 - 3 weeks. Any freelancer with experience in integrating system level codes in VHDL, basics of digital

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    Local
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