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    924 xilinx ofdm jobs found, pricing in USD

    Complete Some task in Digital System Design using Xilinx Vivado Software and Digilent Nexys4 DDR, Task to completed. - Finite-State Machine and Low Power Design - Greatest Common Divisor - LFSR - Creeping Line I will need a screenshot for the following task (Timing diagram and Logic gate design) and a screenshot of past work. N.B: Don't

    $277 (Avg Bid)
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    I already have an m-file that finds the BER of different modulation schemes at different sub carriers and plots the ber vs snr graph . I just need a freelancer to study the mfile/simulink model and include code that uses matlab function 'bertheory' to include the theoretical values in the graph for comparison.

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    ...on Mentor Graphics and Cadence allegro Design Authoring software tools. - Testing knowledge : Lab testing, measurement tools, oscilloscope. - FPGA design knowledge: Vivado(Xilinx), Libero(Microsemi) - Knowledge of PSPICE and LTSPICE simulators - Knowledge of ARINC429, RS845 and ARINC664 interfaces - Knowledge of Aviation standards (or equivalent)

    $31 / hr (Avg Bid)
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    ...read memory on the target computer past the first 4GB because the register holding the address to read memory from is only 32bit. We have a PCI-E development board with a Xilinx Spartan 6 and would like someone to replicate the functionality of the USB 3380 on this development board. Although, the only functionality we need replicated is the ability

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    ...read memory on the target computer past the first 4GB because the register holding the address to read memory from is only 32bit. We have a PCI-E development board with a Xilinx Spartan 6 and would like someone to replicate the functionality of the USB 3380 on this development board. Although, the only functionality we need replicated is the ability

    $10 (Avg Bid)
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    ...read memory on the target computer past the first 4GB because the register holding the address to read memory from is only 32bit. We have a PCI-E development board with a Xilinx Spartan 6 and would like someone to replicate the functionality of the USB 3380 on this development board. Although, the only functionality we need replicated is the ability

    $10 (Avg Bid)
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    need mimo ofdm visible light communication system model performance improvement (transfer rate or bit error rate) (4 sender , 4 receiver , one way communication ) in matlab code (URGENT TASK)

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    inbox me for more details thanks please reply soon i am waiting ...............................................................................................................................................................................................................

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    VPI project . optical coherent ofdm using VPI with matlab co_simulation to reduce PAPR in optical ofdm system

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    VPI project . optical coherent ofdm using VPI with matlab co_simulation to reduce PAPR in optical ofdm system

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    i need a freelancer who is fimiliar with mimo ofdm to build me a matlab code for it

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    inbox me for more details thanks please reply soon i am waiting ...............................................................................................................................................................................................................

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    Given the Open Cores from the open cores project I want a simple module that is able to do the following on a Xilinx ZedBoard: 1. Given 256 bit BITKEY, scramble the input with a hard coded IDKEY in the FPGA and provide a AESKEY 2. The same response needs to be piped to an AES256 module from OPEN CORES in order to encrypt/decrypt a stream of data

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    This is extremely simple but urgent!!! You are asked to provide a simple Xilinx Spartan 6 FPGA program that reads data from multiple I2S input ports and then aggregate them into a single data stream and output through uart or I2s or USB.

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    To implement a MATLAB simulation according to the attached paper about OFDM RADAR.. I want the same figures in the paper

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    UDP data filtering using Xilinx Zynq 7000 family Socs (10 Gb SFP+ port)

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    ...accordingly with the board. I can provide the ucf connection file that shows the connections of the Marvell chip to the fpga. You must work exclusively in VHDL and preferably in Xilinx ISE Suite (however that is up to you as long as the code works). I need this done by Friday 7th July. This is a quick task for someone who knows their work. You will have

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