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    994 xilinx ofdm jobs found, pricing in USD

    ...having difficulties in finishing my final year project. I would like to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor

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    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo

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    OFDM project 1 day left

    writing an OFDM Matlab project

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    Tcp sending on FPGA using verilog xgmii xilinx vivado

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    I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this

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    I would an optisystem project for optical ofdm, (coherent detection, the medium is FSO)

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    Xilinx Ended

    Develop a circuit of SDES(Simplified data enryption standard)

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    need to develop a vhdl code, synthesize the design to get corresponding simulation waveforms by using xilinx (vivado/ise) software.

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    我公司有一个项目, cy7c68013A_128 单片机的软件开发, 细节是用GPIO模仿Jtag烧录两片Xilinx的PROM. (XCF04S, XCF01S). Xilin有比较详细的方案。 见副件。 如果你们承接这类工程, 请你给我一个报价。 我们有硬件平台, 你们需要提供, 1 windows usb 的驱动, 指定等待下载的文件。 Cy7c68013A 的程序,把指定的文件烧录到目标PROM. 启动系统, 读取FPGA内部寄存器,确定烧录成功。

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    I am looking for someone that can program or port an existing Windows or Linux mining program for AMD GPU's to a Xilinx Kintex-7 FPGA I will provide details and Github privately

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    Need a freelancer to port an old Altera(maybe even Xilinx ISE) project into Xilinx Vivado and provide the bitstream to run on a Digilint Zybo Zynq-7010. May be done very quickly since many files are already in a ISE project. Resources: [url removed, login to view] [url removed, login to view]

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    I am looking for a person who will make FPGA NIST5 Cryptocurrency miner. I need full unrolled NIST5 core. NIST5: blake512 -> groest512 -> jh512 -> ke...NIST5: blake512 -> groest512 -> jh512 -> keccak512 -> skein512 Perfect performance: 1x (Example: FPGA at 400MHz clock generates 400Mega Hash / secound) Language: VHDL FPGA: Xilinx 7 series

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    write vhdl code for : 1. (8 16bit register) register file/ a gate-level vhdl models for functional unit. + test benches and simulations. 2. implement a microprogrammed instruction set processor extended on part 1. more details to be given in chat. deadline 28/03/2018

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    attachement is the research plan #Just do Matlab code and description #First generation OFDM as chart 1)Evaluate PAPR 2)Generate PTS 3)Generate SLM Finally apply PTS and SLM to evaluatePAPR Please I wanna perfect work or else i will not pay a anything first show me work for getting pay

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    attachement is the research plan #Just do Matlab code and description #First generation OFDM as chart 1)Evaluate PAPR 2)Generate PTS 3)Generate SLM Finally apply PTS and SLM to evaluatePAPR Please I wanna perfect work or else i will not pay a anything first show me work for getting pay

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    Using a FreeRTOS and lwIP (TCP/IP) on Xilinx ZynQ SoC. Tool is Vivado 16.2 (SDK). At Ethernet interface (PS of ZynQ FPGA), mixed traffic is to be differentiated based on pre-defined IP and Ports and IP packets are to be routed to respective application. Rest all traffic (RAW Ethernet Frames) to be passed on to PL part (FPGA). This can be done by

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    • Target DDR3 controllers development for Frame buffer (on...for Frame buffer (one frame delay) • Features Frame Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document

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    MIMO system has to be designed using MATLAB and report writing

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    We need to develop a QPSK demodulator FPGA xilinx based.

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    write an AI Algorithm for video codec h.264 and design Chip, after design chip of AI Based video codec h.264 you can verify out put on Xilinx FPGA Kit for face recognition in cloud iam expecting this project to finish on or before 26th feb2018 regards D RAMANNA [Removed by Freelancer.com Admin for offsiting - please see Section 13 of our Terms

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