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Master Slave wishbone architecture using I2C-VHDL

This project was awarded to ahmedmohamed85 for $80 USD.

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Project Description

I want a very simple design and simulation of an i2c master controller which can facilitate data transfer between an FPGA device and any external i2c device. Please find attached the document with the diagram of the architecture with the appropriate components to be designed. I want each component designed separately with test-bench stimulus.

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