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Two digits 7-segment display multiplexing logic Design - repost

This project received 15 bids from talented freelancers with an average bid price of $233 USD.

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Skills Required
Project Budget
$100 - $120 USD
Total Bids
15
Project Description

(1). Write VHDL code for entity **1-of-2 multiplexer**, synthesis and implement the design. Present your synthesis result, check summary report and identify the recourses used. Write another architecture description then compare the implementation results.

(2). Write VHDL code for entity **BCD-7-segment converter**, synthesis and implement the design. Present your synthesis result, check summary report and identify the recourses used. Write another architecture description then compare the implementation results.


(3). Write VHDL code for entity **decoder**, synthesis and implement the design. Present your synthesis result, check summary report and identify the recourses used. Write another architecture description then compare the implementation results.

(4). Write the top entity **Two digits 7-segment display multiplexing logic** VHDL code using the above entities as components for the described architecture. Synthesis and implement the design. Present your synthesis result, check summary report and identify the recourses used.


(5). Write a behavioural VHDL architecture description. Synthesis and implement the design and then discuss the results.

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