16-bit modified single-cycle MIPS hardware processor architecture

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Project Description

Project Specification

The objective is to investigate, design and implement a hardware processor architecture to realize a
programming task using the Multimedia Logic Simulator available at:

[url removed, login to view]

The project is to design, implement and test a 16-bit modified single-cycle MIPS
hardware processor architecture (i.e. each instruction is 16-bits in length) to perform the following

“Assume that sixteen random numbers (integers) have been stored into 8-bit data memory locations
(0 through 15) as shown below:

Memory address Contents
0000 02
0001 0A
0002 0F
0003 03
0004 01
0005 07
0006 08
0007 0B
0008 0C
0009 00
000A 04
000B 06
000C 05
000D 09
000E 0E
000F 0D
Sort the numbers into ascending sequence and store the sorted numbers into data memory locations
(16 through 31)”.

Task One
Design a hardware processor with a custom instruction set architecture (i.e. the ISA only needs to
include the instructions you need to perform this specific task) to sort the numbers into ascending
sequence. How many instructions do you have in your ISA?

Task Two
Write a program using the ISA from Task One to sort the numbers into ascending sequence. Store
the program into the processor instruction memory and run the processor. How many clock cycles
does your processor take to complete the task?

Include hardware diagram and program code for Tasks One and Two to be verified.

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