Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers


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    Adder tree 6 days left

    Parameterizable Verilog module that is calculating sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array system.

    $38 / hr (Avg Bid)
    $38 / hr Avg Bid
    1 bids

    Synchronous control of 8 stepping motors with calculation of a trajectory of linear motion and circular motion with constant acceleration for CNC machine. SystemVerilog, FPGA Altera (IntelFPGA)

    $621 (Avg Bid)
    $621 Avg Bid
    5 bids

    Hello, I need a controller for a MAX31855 in Verilog. The controller must be connected to an UART in order to see the data in a terminal. FPGA clock is 50Mhz.

    $67 (Avg Bid)
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    5 bids

    UVM testbench architecture for a synchronous FIFO.

    $64 (Avg Bid)
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    3 bids

    Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed. The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS). The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support soft decision. The Reed Solomon En/Decoder must be set to (223,255) The Interleaver must be parameterizable A Framer/Deframer must add/ remove Headers into the bitstream and should indicate a lock. The Transmit Chain: Data Source(PRBS)-> RS Encoder->Framer->Convolutional Coder- The Receive Chain: Viterbi decoder(soft decoding)->Deframer and Lock detection->RS decoding->PRBS Lock detection and BER Measurement 200 Mbps sustained decoding speed should me maintained. Complete Simulation and HDL sources must be delivered.

    $643 (Avg Bid)
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    11 bids
    Rework of PLC & HMI program 4 days left

    Hello, We want to modify/rework on process of existing PLC & HMI Program built by one freelancer. We will provide previous & new process details, also we will provide program built by freelancer.

    $428 (Avg Bid)
    $428 Avg Bid
    19 bids

    Implement the 4-way handshaking protocol by using SC_METHOD

    $77 (Avg Bid)
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    2 bids

    A Signal Generator should be programmable. A user can use the LCD display and the keyboard to change the: Frequency scale Amplitude scale offset on/off etc.

    $21 (Avg Bid)
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    12 bids

    A (PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. This project is a mere test for the abilities of the bidder. Several Add-On projects will follow. An PSK (BPSK, QPSK, OQPSK, 8-PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. The PSK modulator must have a sampling rate selection between 1ksps-400 MSPS, The PSK demodulator must have a sampling rate selection between 1ksps-200 MSPS,(100 MSPS for BPSK) The developer will develop a PSK (BPSK, QPSK,OQPSK,8-PSK) modulator/ demodulator core . The demodulator core must perform all the carrier and clock recovery mechanisms (costas loop etc.) The PSK modulator will be generate 12 bit I&Q signals and will feed the signals to the demodulator. The Input to the modulator should be a PRBS sequence. The output of the demodulator should be feed to the PRBS Sequence decoder. ( the demodulator should indicate a LOCK) This project is a mere test for the abilities of the [url removed, login to view] are aware that this design can be realized by using Mathworks and Vivado HLS reference designs. If the bidder is sucessfull, we will ask for; A pulse shaping Filter,(TX,RX) A Viterbi decoder(an existing one), Sync Word Insertion, Detection, Reduced Rate FFT, BER count, SNR estimation blocks to be added by the bidder to the existing project for an extra fee.

    $655 (Avg Bid)
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    16 bids

    A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .

    $207 (Avg Bid)
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    7 bids
    MPI Project Expert Needed 2 days left

    MPI Project Expert Needed Regular Work

    $148 (Avg Bid)
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    5 bids

    i have got XY table with two stepper motors. need a code to drive these motors to plot a circle. microcontroler used is atmega8

    $33 (Avg Bid)
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    10 bids

    A stepper motor controller in verilog ,

    $190 (Avg Bid)
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    15 bids
    vhdl expert needed3 1 day left

    Expert in VHDL is needed to do a project

    $27 (Avg Bid)
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    8 bids

    Design software and hardware for measuring voltage, amperage, rpm, temperature, pressure using the "National Instruments Labview.

    $512 (Avg Bid)
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    19 bids

    hello how are you see below text if there are available, find the best tell me at least 1 prominent and 1 complimentary alternative spare the second source which group of two is the best Flow Method IDE ( for below ) ======================= Task#01: research for IOT IDE, Flow Programming method Task#01': research for IC Design IDE/ tools, Flow Programming method Hints: wikipedia related MindMapKeywords_Group_01: embedded system, OS based system, IOT, IC Design MindMapKeywords_Group_02: open source, FREE, Market_Test_version, uptodate Graphical Method

    $28 (Avg Bid)
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    7 bids

    How much it would cost and how much time it may take to build the one shown in link below [url removed, login to view]

    $115 (Avg Bid)
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    2 bids

    I require you to do implementation of ANN or SVM algorithm in Arduino Microcontroller for 1-D EEG signal.

    $103 (Avg Bid)
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    12 bids

    PID Controller Using Particle Swarm Optimization (PSO) for DC-DC converter design a PID Controller using PSO algorithm

    $122 (Avg Bid)
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    16 bids
    MIPS project123 Ended

    MIPS code and assembly language

    $15 (Avg Bid)
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    1 bids