Synchronous control of 8 stepping motors with calculation of a trajectory of linear motion and circular motion with constant acceleration for CNC machine. SystemVerilog, FPGA Altera (IntelFPGA)
Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed. The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS). The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support soft decision. The Reed Solomon En/Decoder must be set to (223,255) The Interleaver must be parameterizable A Framer/Deframer must add/ remove Headers into the bitstream and should indicate a lock. The Transmit Chain: Data Source(PRBS)-> RS Encoder->Framer->Convolutional Coder- The Receive Chain: Viterbi decoder(soft decoding)->Deframer and Lock detection->RS decoding->PRBS Lock detection and BER Measurement 200 Mbps sustained decoding speed should me maintained. Complete Simulation and HDL sources must be delivered.
A (PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. This project is a mere test for the abilities of the bidder. Several Add-On projects will follow. An PSK (BPSK, QPSK, OQPSK, 8-PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. The PSK modulator must have a sampling rate selection between 1ksps-400 MSPS, The PSK demodulator must have a sampling rate selection between 1ksps-200 MSPS,(100 MSPS for BPSK) The developer will develop a PSK (BPSK, QPSK,OQPSK,8-PSK) modulator/ demodulator core . The demodulator core must perform all the carrier and clock recovery mechanisms (costas loop etc.) The PSK modulator will be generate 12 bit I&Q signals and will feed the signals to the demodulator. The Input to the modulator should be a PRBS sequence. The output of the demodulator should be feed to the PRBS Sequence decoder. ( the demodulator should indicate a LOCK) This project is a mere test for the abilities of the [url removed, login to view] are aware that this design can be realized by using Mathworks and Vivado HLS reference designs. If the bidder is sucessfull, we will ask for; A pulse shaping Filter,(TX,RX) A Viterbi decoder(an existing one), Sync Word Insertion, Detection, Reduced Rate FFT, BER count, SNR estimation blocks to be added by the bidder to the existing project for an extra fee.
A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .
i have got XY table with two stepper motors. need a code to drive these motors to plot a circle. microcontroler used is atmega8
Design software and hardware for measuring voltage, amperage, rpm, temperature, pressure using the "National Instruments Labview.
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PID Controller Using Particle Swarm Optimization (PSO) for DC-DC converter design a PID Controller using PSO algorithm