Please I wanna find some who can help me to finish this project as soon as possible, someone who is really expert with FPGA, Verilog HDL and Vivado.
dear sir i am shiv shankar pandit from ludhiana i have requeird my stratgy use in afl formula two zig-zig 1.----zig zag parameeter 0.1 to 5 2. ---position ----- both / only buy / only short / ALL Breakout 3. ---buy = first swing high breakout condition aply -- trade .01 point to 500 point after/ befor and if zig -zag 1 is up then i will take position sell on zig-zag low breakout 0.5 4. --- sell = first low breakout condition aply - trade .01 point to 500 poiont after / befor and if zig -zag 1 is down then i will take position buy on zig-zag high breakout 0.5 5. --target mathod --- none / % / point target 1-- 50 % / 100 % / point varry .01 - 5000 target 2 -- 50 % / 100 % point varry .01 - 5000 6. ---stoploss mathod - non / % / point 7. one clik -- show / hid buy -, exit buy - . short -, exit short show butun on the chart and position crent P/L SHOW ON the chart SEE BELOW ATTACHED FILE REGARD SHIV SHANDIT 7004926136 CALL ME FOR QUAIRY i want to USE this stratgy IN robo treade BACK TESTING IS MUST SHIV SHANKAR PANDIT FROME LUDHIANA-------------7004926136
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I need to implement a system which consists of display, OV7670 camera and zedboard(FPGA board) and should ble to detect multiple faces in input imsge.
Project objectives : This research includes the development of the strong, robust transistor model which will best suitable for the microwave amplifier application. This model can be used to get some linear and nonlinear measurements, which consists of design, development and circuit analysis of HEMT based FET model and also states the experimental result of existing models. Using AWR microwave office tool
The conventional (single-match) priority encoder finds only one match, i.e. the highest priority input. An n-bit MPZ unit finds r (1 ≤ r ≤ n) matches in exactly r cycles. Design an 8-bitMPZ using HDL description. You may use ModelSim or Quartus II software. In your implementation, you may have a mix of behavioral and structural descriptions for modules/components. Slight modifications of the unit, compared to those provided in Section III are allowed. Your report for this problem should include the HDL code of your MPZ design and simulation results to show the correct behavior, or any other interesting observation (e.g. maximum clock frequency of the design).
I have added IEEE paper below. I need following three requirements. 1. project explanation. what is the plan to implement the paper. 2. Implement the paper in matlab. Need matlab simulations 3. Write a verilog code for the paper. Results has to match with matlab simulations.
We need a modification to an Ettus USRP SDR FPGA code. We have a working system and reference for a 1 TX and 1 RX system, using half of the USRP1, including the source files for the FPGA code and corresponding c library. We have working FGPA code for a 2 TX and 2 RX system, and but need about 15 lines of verilog code ported from the 1 TX and 1 RX system to the 2 TX and 2 RX system. Also, we need the working c libary in the transceiver (1 Tx and 1 RX) modified to support the 2 TX and 2 RX configuration, which should require about 20 - 40 lines of c code changes. All work can be completed remotely, and we would make available a reference 1TX and 1RX system (with all source code), and a development environment for the 2TX and 2RX system (where you could test your modified FGPA code and c code).
We would need design and production of FPGA or ASIC units optimized to run just a specific OpenCL program as fast as possible. This OpenCL program calculates cryptographic hash functions and has a benchmark report that displays how many hash calculations are made per second. Your FPGA/ASIC should calculate at least 20 billion hashes per second while executing our OpenCL kernel, and should consume less than 1500W. The software in question is here: [url removed, login to view] and the OpenCL kernel that needs to be executed in hardware by your device is the /zcash/gpu/[url removed, login to view] source file. We would prefer that you provide OpenCL drivers for Windows 32-bit , but we can discuss the possibility to switch to Linux. The device interface can be USB or PCI-e or other , there are no constraints for that. Important: Our budget will vary depending on the actual performance of your device. Benchmark is measured by the application itself and verified by a server, and we will test together the actual performance achieved before releasing our payments. Thanks