Filter

My recent searches
Filter by:
Budget
to
to
to
Skills
Languages
    Job State
    31 jobs found, pricing in USD

    We are looking for designer to design Video object tracking : 1- FPGA based platform . 2- ANalog and Digital video source . 3- Cross correlation . 4- Centroid . 5- Edge . 6- Multitarget Detection . 7- Moving Target Indicator . 8- Image Stabilization . 9- Move on Move tracking . 10- Low latency .

    $1049 (Avg Bid)
    $1049 Avg Bid
    14 bids

    Hi luvtomar, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $50 (Avg Bid)
    $50 Avg Bid
    1 bids
    Project for sgostantian 7 days left
    VERIFIED

    Hi sgostantian, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $78 (Avg Bid)
    $78 Avg Bid
    1 bids
    Project for fattouma92 7 days left
    VERIFIED

    Hi fattouma92, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $78 (Avg Bid)
    $78 Avg Bid
    1 bids

    Hi profpgarammer, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $70 (Avg Bid)
    $70 Avg Bid
    3 bids

    I would like to hire a developer who can work exceptionally well in VHDL and is good in algorithms and matlab

    $117 (Avg Bid)
    $117 Avg Bid
    14 bids

    I am looking for a senior electronics engineer to assist with the design and layout of a low noise circuit for the raspberry PI. Experience in the RF industry would be useful but not essential.

    $626 (Avg Bid)
    $626 Avg Bid
    32 bids

    We need a modification to an Ettus USRP SDR FPGA code. We have a working system and reference for a 1 TX and 1 RX system, using half of the USRP1, including the source files for the FPGA code and corresponding c library. We have working FGPA code for a 2 TX and 2 RX system, and but need about 15 lines of verilog code ported from the 1 TX and 1 RX system to the 2 TX and 2 RX system. Also, we need the working c libary in the transceiver (1 Tx and 1 RX) modified to support the 2 TX and 2 RX configuration, which should require about 20 - 40 lines of c code changes. All work can be completed remotely, and we would make available a reference 1TX and 1RX system (with all source code), and a development environment for the 2TX and 2RX system (where you could test your modified FGPA code and c code).

    $1196 (Avg Bid)
    $1196 Avg Bid
    16 bids

    We would need design and production of FPGA or ASIC units optimized to run just a specific OpenCL program as fast as possible. This OpenCL program calculates cryptographic hash functions and has a benchmark report that displays how many hash calculations are made per second. Your FPGA/ASIC should calculate at least 20 billion hashes per second while executing our OpenCL kernel, and should consume less than 1500W. The software in question is here: [url removed, login to view] and the OpenCL kernel that needs to be executed in hardware by your device is the /zcash/gpu/[url removed, login to view] source file. We would prefer that you provide OpenCL drivers for Windows 32-bit , but we can discuss the possibility to switch to Linux. The device interface can be USB or PCI-e or other , there are no constraints for that. Important: Our budget will vary depending on the actual performance of your device. Benchmark is measured by the application itself and verified by a server, and we will test together the actual performance achieved before releasing our payments. Thanks

    $5407 (Avg Bid)
    $5407 Avg Bid
    6 bids

    Em chào anh ạ, em tên là Thu Huyền Hiện tại bên công ty Nhật Bản bên em, có nhu cầu muốn tuyển nhân viên làm việc tại Nhật Bản 3 năm, sau đó về Việt Nam phát triển tiếp ở Hà Nội. Lương làm việc tại Nhật Bản là 4000$, kèm các phụ cấp, chế độ ạ. Nội dung công việc thì em đọc thấy anh rất thích hợp với chuyên môn nghề nghiệp của anh. Không biết anh có quan tâm đến vị trí bên em không ạ? Hoặc anh có quen biết ai có quan tâm thì anh có thể giới thiệu giúp em ạ, SĐT của em là: 0909 051 764. Em cảm ơn anh ạ.

    $250 (Avg Bid)
    $250 Avg Bid
    1 bids
    $144 Avg Bid
    4 bids

    I need a PCB card with CMOS sensor readout over 16 LVDS channel. Data gathered will be compressed ([url removed, login to view] compression) and data output will be over USB 3.0 and/or GigE (both interfaces will be available and working on the board)

    $2388 (Avg Bid)
    $2388 Avg Bid
    6 bids
    FPGA, circuits Ended
    VERIFIED

    FPGA, circuits plan. Projects plan, writings... more in PM

    $20 / hr (Avg Bid)
    $20 / hr Avg Bid
    24 bids

    Hi, The vision I have in mind is comparable to a machine vision camera. CMOSIS CMV2000/4000 cmos sensor will be readout over LVDS channels and acquired data compressed with H264 encoder (MPEG 4) and compressed data will be send over GigE and/or USB 3.0. I'm a PCB designer with RF design experience, for this project: 1. Propose design architecture ( Pure FPGA, FPGA+controller, DSP or SoC FPGA etc.) 2. PCB Design 3. Software or VHDL project You can quote for total or for each parts.I can design and verify second part myself if it is needed. -1920x1080 (minimum) -Large Pixel Cells [url removed, login to view] x [url removed, login to view] (CMV2000, CMV4000 sensors) -50 fps (minimum, optional 150 fps) -MPEG 4 compressed over GigE and/or USB3.0 interface

    $2902 (Avg Bid)
    $2902 Avg Bid
    6 bids

    FPGA 医疗成像,和视频融合 ,可视化KVM ,video wall 视频处理(Removed by [url removed, login to view] Admin)

    $20008 (Avg Bid)
    $20008 Avg Bid
    13 bids

    I need a few suggestions on how to fix my project, schematic file created in quartus 13.1

    $141 (Avg Bid)
    $141 Avg Bid
    13 bids

    There are two signals, A and Z. During a certain period, Z will always be low, and go high only once. Between any two Z pulses, there will be x A pulses. The purpose of this project is to determine the number of A pulses and the 'even-ness' of the A pulses; whether they're of uniform length during both high as well as low phase; the average high-to-low and low-to-high timings of each A pulse must be determined. This data must be then transferred via serial communication to a PC (using RS485). It is perfectly acceptable to dump raw data to the PC and do all the processing on the PC itself. The average frequency of the A signal will be range between 10 and 50 Khz. The frequency of Z is the same, in the sense of how long Z will remain 'high' before falling back to 0, but it will pulse only once per cycle. Z can be seen as a delimiter indicating the start of each cycle; the data to be collected is for the A signal for the duration of a single such cycle.

    $391 (Avg Bid)
    $391 Avg Bid
    10 bids

    I would like to hire a developer who can work exceptionally well in VHDL and is good in algorithms

    $353 (Avg Bid)
    $353 Avg Bid
    14 bids

    I need help to simulate rigid body fracture with surface meshes for any object in C++ language in visual studio

    $292 (Avg Bid)
    $292 Avg Bid
    3 bids

    ************** I P U D P R O U T I N G *************************** I have dedicated server with fresh installation Uuntu/Debian LEMP with root privileges with 1 main IP and 5 additional IPs. At this moment outbound requests are routeet always over 1 IP - main IP. To check it I use website [url removed, login to view] Inbound works correctly. I need reconfigure IP routes to set it's own IP for every additional IP in outbound requests. The succes conditions: - remote IP on external website [url removed, login to view] = real additional IP - properly works all protocols (http, ftp...) - properly works all methods (post, get...) - results of requests return to the correct ip (virtual host configured over nginx). Server have not any admin panel so you must be strong in network administration using commands. What I'm not intersted at this moment and what isn't succes: - advice to use CURLOPT_INTERFACE, - advice to use proxy, - every configuration works what are unnecessary to resolve problem like security, users etc. (It is test server). ****************************************************************************************************************** S I M P L E D E S C R I P T I O N O F P R O B L E M I have 6 IPs: [url removed, login to view] -> main [url removed, login to view] -> additional [url removed, login to view] -> additional [url removed, login to view] -> additional [url removed, login to view] -> additional [url removed, login to view] -> additional You can 5 virtual hosts configured in nginx (or you can configure it if you want). ------------------------------------------------------------------------------------------------------------------ C U R R E N T S I T U A T I O N I have problem with outbound. Using PHP cURL and phantomjs: - when I I'm sending requests to website [url removed, login to view] using virtual host and IP [url removed, login to view] I get result IP [url removed, login to view] - when I I'm sending requests to website [url removed, login to view] using virtual host and IP [url removed, login to view] I get result IP [url removed, login to view] ....... - when I I'm sending requests to website [url removed, login to view] using virtual host and IP [url removed, login to view] I get result IP [url removed, login to view] ------------------------------------------------------------------------------------------------------------------ W H A T D O I W A N T T O A C H I E V E ? Using PHP cURL and phantomjs: - when I will send requests to website [url removed, login to view] using virtual host and IP [url removed, login to view] I want get result IP [url removed, login to view] - when I will send requests to website [url removed, login to view] using virtual host and IP [url removed, login to view] I want get result IP [url removed, login to view] ........ - when I will send requests to website [url removed, login to view] using virtual host and IP [url removed, login to view] I want get result IP [url removed, login to view]

    $143 (Avg Bid)
    $143 Avg Bid
    11 bids