We got a requirement on ASIC Design or Verification Engineer, If you or any of your friends are looking for job Change, please share your update profile to [Removed by Freelancer.com Admin] Job Description as follows Requirements: • Experience: 2 - 10 Years of Experience in ASIC • Qualification: BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Pune. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience in developing test plan and Coverage plan for IP’s in ASIC. • Hands on experience in developing test bench include test bench components, Functional/Code/Netlist coverage model, and Test cases and verify the functionality of complex IP blocks in ASIC. • Good hands-on expertise in scripting languages Perl/Python/TCL. Interested Professionals with minimum of 2 years of experience can send their Updated profiles to [Removed by Freelancer.com Admin] Along with below details. All the details would be help full. Current Employer (Company) Name : Designation: Presently working on : ASIC Design or Verification Skills : Total years of Experience: Relevant Experience: Cost to the company (Salary per annul): Expected Salary: PAN No: Notice period to Current Employer: Negotiable notice period: Current Location: Contact Number: Email Id: Skype ID (if available): Please send these details as soon as possible.
write vhdl code for : 1. (8 16bit register) register file/ a gate-level vhdl models for functional unit. + test benches and simulations. 2. implement a microprogrammed instruction set processor extended on part 1. more details to be given in chat. deadline 28/03/2018
Hi Duc D., I noticed your profile and I am considering offering you my FPGA project. Off the bat I would like to offer you 50$ for an hour of your time to develop a plan and budget for this work. We can discuss further details over chat after you have reviewed my specification document. I hope this project sounds interesting to you and I am able to send the required hardware to you if we decide to go forward.
-This must be done on System Verilog NOT Verilog. -Need to be able to input random data and have results. -Need Explanation for every step taken and code written. (reason why you used the code and math -behind it) -Must have everything Required in the attachment. -Must be able to explain to someone with zero understanding of the topic This is a learning experience for me so please have lots of explanations. Must have Soft paper written formulas and designs.
The main purpose is to design a system which can measure shock or acceleration in athletes which is caused when running using STM32F4 evaluation board and associated boards. Generally athletes apply huge amount of shock or acceleration forces (g-forces) on some particular bones such as shin bones and leg muscles for every impact with ground. If the shock is iterates above specific thresholds can lead to permeant injury and it often goes unnoticed by the athlete until the damage has already reaches the top-tier and so a system is required to avoid this damage which can monitor, record and alert the athlete if the shock levels goes above the threshold.
Parallel Computing with GPUs Parallel Computing with GPUs
I would like to have a fully documented simulation of an electrostatic actuation of a mems structure. The mems structure is described in the attached document. I am interested to know the deflection and stress with respect to the applied voltage. All simulation should be done by an *open source software of your choice*. Please also include a tutorial on how to set up the open source software.
I need the design / schematic for a composite instrument in order to measure insulation and dielectric strengh. megaohmeter section: - measurement voltage: programmable, from 100V to 3000V dc - insulation resistance range: 200Kohm to 200Gohm autorange - 1% accuracy dielectric strengh section: - testing voltage: to 6000Vdc, 3% accuracy - maximum current 5mA - current measurement: 1% accuracy the two sections must share the high voltage generator part only the analog part is required (voltage and current generation, amplifiers...), i will complete the instrument with the microprocessor part, providing the necessary analog and digital I/O
Choose an algorithm of Random Number Generator and develope high-performance computing architecture of the chosen algorithm using the Electronic Design Automation tools. Write a program and integrate with a hpc scheme simulator.
Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed. The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS). The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support soft decision. The Reed Solomon En/Decoder must be set to (223,255) The Interleaver must be parameterizable A Framer/Deframer must add/ remove Headers into the bitstream and should indicate a lock. The Transmit Chain: Data Source(PRBS)-> RS Encoder->Framer->Convolutional Coder- The Receive Chain: Viterbi decoder(soft decoding)->Deframer and Lock detection->RS decoding->PRBS Lock detection and BER Measurement 200 Mbps sustained decoding speed should me maintained. Complete Simulation and HDL sources must be delivered.