Verilog / VHDL Jobs

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About Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    27 jobs found, pricing in USD
    MPI Programming , Parallel programming ,MPI graphs 6 days left
    VERIFIED

    Hello I would like help with MPI graphs MPI Programming , Parallel Programming , Protocol Tarry, Protocol Echo

    C++ Programming CUDA Java Parallels Automation Verilog / VHDL
    $102 (Avg Bid)
    $102 Avg Bid
    2 bids
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    Compiler Design 6 days left

    I need to compile a programming language to output quadruples for variable declaration and assignment statement using c plus plus

    C Programming C++ Programming Java Software Architecture Verilog / VHDL
    $25 (Avg Bid)
    $25 Avg Bid
    3 bids
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    VLSI (Microwind) software 5 days left
    VERIFIED

    need to improve skills using Microwind software

    C Programming Electronics Engineering Software Architecture Verilog / VHDL
    $12 / hr (Avg Bid)
    $12 / hr Avg Bid
    1 bids
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    Microprocessor systems help 5 days left

    you are required to create your own device. You are allowed to chose your own topic, however, it should meet the minimum requirements listed below. There will be points distributed for creativity, keep that in mind. Your setup should feature microcontroller to microcontroller communication. Additionally you must use at least 3 of the following systems: Matrix based input Matrix based output Tim...

    Electrical Engineering Electronics Microcontroller Verilog / VHDL Wireless
    $40 (Avg Bid)
    $40 Avg Bid
    4 bids
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    Design a counter using Quartus II ( VHDL ) 5 days left

    Design a counter for the KL shopping mall entrances to allow maximum 99 shoppers at a time to promote social distancing. [Hints: Reset button can be used to clear the counter every morning; in/out signal can be used to control the up/down counter while people are moving in and out; red-light can be used to indicate whether they are allowed to enter] The report should include the following : -...

    Altera Quartus Digital Design Verilog / VHDL
    $30 (Avg Bid)
    $30 Avg Bid
    2 bids
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    Parsing Infix notation to ONP - Verilog [FGPA] 5 days left

    Parsing Infix notation to ONP i Verilog [FGPA] and calculating the value in two modules

    FPGA Verilog / VHDL
    $30 (Avg Bid)
    $30 Avg Bid
    2 bids
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    Xilinx FPGA Expert 4 days left
    VERIFIED

    Xilinx SOC expert is required for a line of projects focusing on AI as a service, where we will build a SOC based server accessible from the cloud. The ideal candidate needs to be experienced with VIVADO, VITIS, HLS, and OpenCL. The ideal candidate must be an AXI4 expert and has real life experience with HLS, we will not teach anybody what's HLS and how he is supposed to use it, so please onl...

    C Programming Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $562 (Avg Bid)
    $562 Avg Bid
    4 bids
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    Rewrite C code to make it synthesizable to simulate in HLS tool - Tongue Segmentation 3 days left
    VERIFIED

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    C Programming JavaScript PHP Verilog / VHDL
    $170 (Avg Bid)
    $170 Avg Bid
    2 bids
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    One Simulator Expert 3 days left
    VERIFIED

    - Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator

    C Programming Certified Information Systems Security Professional (CISSP) Cisco Network Administration Verilog / VHDL
    $215 (Avg Bid)
    $215 Avg Bid
    3 bids
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    HLS Tools VHDL Expert C Programmer 3 days left
    VERIFIED

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    C Programming Electronics Verilog / VHDL
    $143 (Avg Bid)
    $143 Avg Bid
    5 bids
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    Write C code to make it synthesizable to simulate in HLS tool - Tongue Segmentation 3 days left
    VERIFIED

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    C Programming Electrical Engineering Software Architecture Verilog / VHDL
    $140 (Avg Bid)
    $140 Avg Bid
    4 bids
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    electronical eng very small project (signal) 3 days left
    VERIFIED

    I need help person who know this subject -Signal Exponential sin and cos unit step dirac Delta Shifting and scaling of signal -systems linarity LTI system convolution -furier transforms -modulation teory

    Electrical Engineering Electronics Matlab and Mathematica Signal Processing Verilog / VHDL
    $18 / hr (Avg Bid)
    $18 / hr Avg Bid
    8 bids
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    Rewrite C code to make it synthesizable to simulate in HLS tool - Tongue Segmentation 3 days left
    VERIFIED

    About the manual RTL design approach is that mean i need scratch the RTL refer to the c code given or i can do manual modifications in the ready RTL (generate after synthesis)? Or depends to myself? Either both way also ok? For the current moment, u r free to choose any method as long as u feel comfortable and the method is *efficient*, and meet the goal of *design optimization*. Therefore, you ...

    C Programming JavaScript PHP Verilog / VHDL
    $156 (Avg Bid)
    $156 Avg Bid
    6 bids
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    One Simulator Expert 3 days left
    VERIFIED

    - Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator

    Certified Information Systems Security Professional (CISSP) Cisco Engineering Network Administration Verilog / VHDL
    $140 (Avg Bid)
    $140 Avg Bid
    1 bids
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    design OPAMP integrator using two stage CMOS amplifier in cadence Virtuoso tool 3 days left

    Duration 1 week, expected cost 7k

    Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL
    $8 - $21
    $8 - $21
    0 bids
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    adaptive cruise control using arduino on simulink 3 days left

    Adaptive Cruise Control Objective Use Simulink environment to develop and implement an adaptive cruise control system for vehicles that automatically adjusts the vehicle speed to maintain a safe distance from vehicles ahead. Hardware Arduino uno x 1, button x 5, distance sensor x 1, 4 digit 7-segment anode display x 1 Description Implement an adaptive cruise control system with five buttons of (1...

    Arduino Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $102 (Avg Bid)
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    6 bids
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    an expert on verilog, QUARTUS and MODELSIM 3 days left
    VERIFIED

    I need someone who knows verilog hdml, quartus and modelsim.

    Altera Quartus Digital Design Digital Electronics Electrical Engineering Verilog / VHDL
    $21 (Avg Bid)
    $21 Avg Bid
    8 bids
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    My project 3 days left

    Hi I need an expert for the optimization of PSO. This system is an inverted pendulum system that uses Sliding Mode Control (SMC) to stabilize the inverted pendulum output. And as an addition, I want to use the Particle Swarm Optimization to get the best 'lamda' value which is the sliding surface coefficient, thus, optimizing the output. The SMC controller and the inverted pendulum system...

    Electrical Engineering Electronics Engineering Matlab and Mathematica Verilog / VHDL
    min $50 / hr
    min $50 / hr
    0 bids
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    Xilinx FPGA coding 2 days left
    VERIFIED

    Xilinx SOC expert is required for a line of projects focusing on AI as a service, where we will build a SOC based server accessible from the cloud. The ideal candidate needs to be experienced with VIVADO, VITIS, HLS, and OpenCL. The ideal candidate must be an AXI4 expert and has real life experience with HLS, we will not teach anybody what's HLS and how he is supposed to use it, so please onl...

    Arduino C Programming Electronics Microcontroller Verilog / VHDL
    $644 (Avg Bid)
    $644 Avg Bid
    8 bids
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    Digital signal processing 1 day left

    need a DSP teacher for a project

    Digital Signal Processing Electrical Engineering Electronics Matlab and Mathematica Verilog / VHDL
    $14 (Avg Bid)
    $14 Avg Bid
    5 bids
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    circuit design and coding -- 2 1 day left
    VERIFIED

    I have a project about circuit design + coding + teaching me how to do it hardware and telling me the components it is about current leakage detector. need to finish the design and coding by today. my budget is 30-60$

    Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL
    $58 (Avg Bid)
    $58 Avg Bid
    7 bids
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    Clock recovery model 1 day left
    VERIFIED

    Debugging a clock recovery model in verilog

    Circuit Design FPGA Telecommunications Engineering Verilog / VHDL Wireless
    $21 (Avg Bid)
    $21 Avg Bid
    3 bids
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    PLC Programmer 18 hours left

    We are looking for a PLC programmer to develop a new programing ladder for operation of our seamwelding unit using Siemens of Allen Bradly units. The program will involve programing operation of approximately analog/digital I/Os.

    Electrical Engineering Electronics Microcontroller PLC & SCADA Verilog / VHDL
    $1093 (Avg Bid)
    $1093 Avg Bid
    48 bids
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    Tiny odification on a verilog model 12 hours left
    VERIFIED

    Do NOT big if you don't have the knowledge. This task is simple but it needs some background so you don't have to spend too much time to think about it if you have the strong knowledge ok! I have a model for a clock recovery including encoder/decoder with the emphasis to the decoder, the decoder needs to estimate the clock from the data, the model already does this job but I need to add ...

    Circuit Design Electrical Engineering FPGA Verilog / VHDL Wireless Radio Frequency Engineering
    $18 (Avg Bid)
    $18 Avg Bid
    6 bids
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    logic design expert for me 6 hours left
    VERIFIED

    must be extremely expert in : CMOS transistor networks Noise Margins Analysis of Sequential Circuit, State Diagram, Dead states, Synchronizers Synthesis of Sequential Circuit, Min Length and One-Hot encoding Synthesis, Mealy vs Moore Combinational Loops, State minimization The D Flip-Flop, shift registers, KMAPS/ SOP/ POS Transmission Gates (4-8 problems)

    Circuit Design Electrical Engineering Engineering Software Architecture Verilog / VHDL
    $121 (Avg Bid)
    $121 Avg Bid
    10 bids
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    I want to appoint a mips programmer to solve two question for me in 2 hours 2 hours left

    The question will be basic question like using function call, loop etc type to solve any polynomial equation or print string etc

    Assembly C Programming Engineering Verilog / VHDL x86/x64 Assembler
    $2 / hr (Avg Bid)
    $2 / hr Avg Bid
    2 bids
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    Seo para smartivhd.com 3 days left

    oi, preciso de seo para [login to view URL], quero a melhor classificação no [login to view URL] globalmente, qualquer um pode me dar bons resultados palavras-chave, melhor provedor de iptv nos EUA, melhor provedor de iptv no Canadá, melhor provedor de iptv em u

    Internet Marketing SEO SEO Auditing Verilog / VHDL
    $257 (Avg Bid)
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    39 bids
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