Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    14 jobs found, pricing in USD

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    $54 (Avg Bid)
    $54 Avg Bid
    4 bids

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting and growing Blockchain Technology + No cont...

    $15 / hr (Avg Bid)
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    4 bids
    Vivado HLS Expert 5 days left
    VERIFIED

    I am willing to pay for only Vivado HLS expert. Will discuss via interview.

    $1345 (Avg Bid)
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    8 bids

    The project requires hardware & software design, implementation and testing of a simple & basic multi-function digital clock using Zynq 7000 ZED board. See attached for further information and specifications.

    $449 (Avg Bid)
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    10 bids

    i need to build a Gaussian elimination by MIPS

    $53 (Avg Bid)
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    13 bids
    FPGA with server 5 days left

    create a web api connect to the fpga cyclone v (altera de10-standred) , then altera can response to hte request change connect some point with each other.

    $547 (Avg Bid)
    $547 Avg Bid
    5 bids

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
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    4 bids

    General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Ba...

    $50 (Avg Bid)
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    8 bids

    Here projects are implemented in VHDL programming using Xilinx software. B.E/[login to view URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

    $153 (Avg Bid)
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    2 bids

    Please read all the details first. and I will create 45% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer...

    $753 (Avg Bid)
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    1 bids

    Looking for automation and PLC programmer to control and program motor cycles with PLC for user input on speed and time. Have not picked out which PLC but looking into something like AutomationDirect.

    $2086 (Avg Bid)
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    18 bids

    Hello, I made a code that creates an interface between the MSP430 and a 128x32 OLED, all the code is perfectly functional. I need help loading fonts with different sizes (small, medium , large). Requirements for assigning this project: Have MSP430 or MSP432; Have an OLED display;

    $25 (Avg Bid)
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    2 bids

    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit should be initialized with a high-active rese...

    $43 (Avg Bid)
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    11 bids

    Digital Circuit will be represented and simulated via ModelSim simulator. Consider the digital circuit represented below. Two eight-bit wide data input ports are added. The result is then used to set one of eight output lines according to predefined thresholds. Code this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the...

    $28 (Avg Bid)
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    11 bids