Very-large-scale integration (VLSI) jobs

Filter

My recent searches
Filter by:
Budget
to
to
to
Skills
Languages
    Job State
    10 jobs found, pricing in USD

    Multiplier cell design with the application of 8X8 multiplier, related to VLSI design (very large scale integration). required : some report corrections in chapter 1 and 2 regarding the references and report writing. I have a attached a copy of the report and a paper specifying the corrections.

    $21 (Avg Bid)
    $21 Avg Bid
    6 bids

    Multiplier cell design with the application of 8X8 multiplier, related to VLSI design (very large scale integration). required : some report corrections in chapter 1 and 2 regarding the references and report writing. I have a attached a copy of the report and a paper specifying the corrections.

    $23 (Avg Bid)
    $23 Avg Bid
    4 bids

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

    $555 (Avg Bid)
    $555 Avg Bid
    5 bids

    Need someone to verify a memory controller using UVM environment. CAN bus is used as a memory cycle initiator and write/read burst transactions need to be verified.

    $375 (Avg Bid)
    $375 Avg Bid
    5 bids

    I want to design OTA in Cadence vituoso with 180 nm Technology and some other specification

    $225 (Avg Bid)
    $225 Avg Bid
    2 bids

    In this project numerically simulated Dual material Double gate MOSFETs structure through ATLAS device simulator. Analysis and comparative study of the electrical characteristics of DMDG MOSFETs with that of conventional SOI MOSFETs has been done. DMDG MOSFETs has become a important part of VLSI research. An analytical model is developed using ATLAS simulator to analyze short channel effects (SCE),threshold voltage, potential [url removed, login to view] structure was designed and some possible errors were optimized

    $9 - $23
    $9 - $23
    0 bids

    Looking for an expert to join my team with expert level integration REST api and ETL experience. Not looking for " I am so F****ng experience, 4 years, I know life, I know it all" type of people. Those can go "F****" themselves. Looking for Qualities below: 1) Honest 2) Driven to be a part of something awesome 3) Self-starter 4) Ability to work fast, dynamic and creative. 5) Long-term 6) If you are money hungry, you are not for me. 7) If you are dedicated and want to make something of your life, then send me your resume. Otherwise don't bother please, or waste my time. --> "P.S. If you are passionate about what you do, you will have the money regardless - I am building a team. And already very successful. Don't send me bullshit please. Need to build a process (approach) for integration with workday, peoplesoft, SAP, iCims, TriNet, quickbooks and others who offer rest APIs. Need person who is willing to win big, and be good. Not chin-up, conceited, egoistic mo-fos. I am Silicon Valley. Building a good strong team with a good chunk of investment. Prove yourself, too many fake professionals out there. This is a small project. I need the candidate to know integration concepts and can grasp the idea and quickly put things together without much guidance. Without BRDs. I am not Elon Musk - but follow similar values. Bid only if read above. I don't care about your experience. I have a team, looking for special skills in blockchain, AI (tensorflow), video editing/presentations/voiceovers. I am looking for a hardworking warm-hearted, positive and trustworthy person. You know who you will be... I am not in a rush. Please have a resume ready with your bid.

    $27 (Avg Bid)
    $27 Avg Bid
    5 bids

    FIND THE ATTACHED IEEE [url removed, login to view] REQUIREMENTS

    $86 (Avg Bid)
    $86 Avg Bid
    4 bids

    Future technologies will allow the integration of hundreds of billions of transistors on a single chip allowing the fabrication of chips with hundreds of processing cores. So, IC designers should focus on the communication between these cores in order to meet the design requirements in terms of speed, area, power consumption, and time to market constraints. Using conventional parallel buses to transmit data on-chip is not efficient anymore in terms of area, given that in new technologies interconnects do not scale at the same rate as transistors do, and in terms of power due to the large number of drivers, repeaters, and buffers. Also, parallel buses suffer from timing errors due to jitter, and cross talk that eventually limit the performance. One of the solutions to solve these on-chip communication issues is to replace conventional parallel buses with serial links. Many publications already proposed solutions based on serial links, and dealt with the intersymbol interference on their interconnects using equalization, frequency translation using high frequency carrier signal or using data encoding, or using resistive terminated interconnects. In this project, the transmitter section of the SerDes device is discussed. It consists of serializer and Three Level Encoder. Serializer transmits parallel data into serial data. Then this data is passed to Three Level Encoder. Three Level Encoder maintains the DC level of the signal. It is used to embed the clock and data. Serializer is implemented with two types of techniques one is simply by using MUX and another is by using DETFF. Limitation of MUX is overcome by DETFF.

    $427 (Avg Bid)
    $427 Avg Bid
    2 bids

    Project objectives : This research includes the development of the strong, robust transistor model which will best suitable for the microwave amplifier application. This model can be used to get some linear and nonlinear measurements, which consists of design, development and circuit analysis of HEMT based FET model and also states the experimental result of existing models. Using AWR microwave office tool

    $23 - $196
    $23 - $196
    0 bids