ASIC Design & Verification Interview Panel required urgently
- Status Closed
- Budget N/A
- Total Bids 4
Bachelors in Engineering from a reputed institute with good academic record
Having 6+ years experience in ASIC design & verification
Good Knowledge on Tools like VMM, UVM, OVM, VERA Preferable SOC Verification.
ASIC design experience with RTL coding in Verilog/VHDL, FPGA experience, FPGA Board bring, FPGA synthesisGet free quotes for a project like this
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