To experience the design issues of advanced computer architectures through the design of an analyzer for a simplified MIPS CPU using high level programming languages. The considered MIPS CPU adopts the CDC 6600 scoreboard scheme to dynamically schedule in

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We have to write code either in VHDL or in C/C++ for computer architecture. In this project we need to implement CDC 6600 scoreboard scheme of dynamic instruction scheduling and using cache for load and store instruction for cache hit and cache miss.

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