In this project, you will implement a flexible cache and memory hierarchy simulator and use it
to study the performance of memory hierarchies using the SPEC benchmarks.
In Part A, you designed a generic cache simulator module with some configurable parameters.
This cache module can be instantiated (used) as an L1 cache, an L2 cache, or an L3 cache, and
so on. Since it can be used at any level of the memory hierarchy, it will be referred to
generically as CACHE throughout this specification. In Part B, you will design a flexible two level
memory hierarchy simulator with certain extensions using the CACHE module designed in Part-
Both simulators will take an input in a standard format which describes the read/write requests
from the processor. Simulator output is also expected to be in a standard format as explained in
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