FPGA based data logger

  • Status Closed
  • Budget N/A
  • Total Bids 18

Project Description

We require a FPGA based data logging system that simultaneously captures 20 channels of high speed RS422 data at a very high baud rate.

Data capture:

• Able to continuously capture data and timestamp from 20 separate RS422 channel input lines, each of which consists of 3 encoded channels (X,Y,Z) of 6 bytes total at 230400 baud (or above if necessary to achieve a 5 KHz sampling rate)

• Capability to send commands (sample trigger etc) to remote capture boards on common RS422 Tx bus

• Capability to store data synchronised with NEMA GPS position and time data

• Capability to store a tacho synchronisation signal from a digital input line

Data storage:

• Direct storage to standard SD card using Windows file system

• SATA drive storage using windows formatted SATA solid state drive. Drive must be able to be swapped to PC and files accessible using windows file system

• Continuous cyclic overwrite capture mode with data amplitude trigger level function to cause section of data to be permanently stored

• Continuous record mode whereby system records until media full then illuminated alarm LED output line

PC connectivity:

• Ethernet TCP/IP connectivity for live and recorded data feed to PC software

• USB 2.0 PC connectivity for live data feed to PC software (not essential)

We also require the coder to produce a simple PC GUI to communicate with the FPGA board over Ethernet and optionally USB 2.0

PC software:

• Capable of displaying recorded and live data

• Recorded data should be able to be selected based on time, trigger event or GPS location.

• Capable of setting sensor board options via common RS422 Tx bus

• Capable of displaying channel info (scale, units etc)

• Capable of exporting selected blocks of data to CSV format

• FFT window to show frequencies present in live or selected sections of recorded data

It is intended to upgrade the design to allow the encoding and storing of digital video from IP camera(s) so the choice of FPGA should reflect this.


• Well documented VHDL/Verilog.

• Any embedded core code.

• Circuit schematic

• Well documented Windows PC source code for GUI

• Compiled PC GUI

• Instructions to set up and program FPGA with supplied code.

We suggest coder bases primary design around a FPGA demo board which will make it easy for them and us to collaborate using same hardware for testing.

We already have working RS422 X,Y,Z accelerometer boards that can be provided to test with when required.


Upon project completion, and provided the coder is capable, we may post another project for the coder to design a PCB layout from the provided schematic.


Coder should be able to demonstrable previous successful projects in advanced FPGA design with previous FPGA embedded projects that have utilised Windows file system on hard drives, Ethernet TCP/IP communications and RS232 transmission and reception.

Coder should give regular progress updates (twice a week) and ask if there are any ambiguities.

Coder should speak fluent English and be available via telephone and/or Skype.

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