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Master Slave wishbone architecture using I2C-VHDL

I want a very simple design and simulation of an i2c master controller which can facilitate data transfer between an FPGA device and any external i2c device. Please find attached the document with the diagram of the architecture with the appropriate components to be designed. I want each component designed separately with test-bench stimulus.

Skills: Electronics, Microcontroller, Verilog / VHDL

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About the Employer:
( 0 reviews ) Hatfield, United Kingdom

Project ID: #4289387

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ahmedmohamed85

Dear sir, I have more than 5 years experiance in VHDL programming please check you PM

$80 USD in 4 days
(21 Reviews)
5.5

4 freelancers are bidding on average $158 for this job

Tauseef240

Hi, I am MSc in VLSI design and can do this work.

$200 USD in 5 days
(11 Reviews)
4.5
noumanmehtab86

i can help please check ur pm.

$250 USD in 7 days
(2 Reviews)
1.8
tamasgy89

Hi, I have 5 years VHDL and digital design experience. I'm experienced with component-level testbench design and with ModelSim simulation as well. I'm more than happy to deliver this project to you. Thanks!

$100 USD in 10 days
(0 Reviews)
0.0