Master Slave wishbone architecture using I2C-VHDL
- Status Closed
- Budget N/A
- Total Bids 4
I want a very simple design and simulation of an i2c master controller which can facilitate data transfer between an FPGA device and any external i2c device. Please find attached the document with the diagram of the architecture with the appropriate components to be designed. I want each component designed separately with test-bench stimulus.Get free quotes for a project like this
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