Solve a bug on Verilog on NetFPGA board implementation (access to 2 NetFPGAs required) - repost
- Status Closed
- Budget N/A
- Total Bids 3
We need a Verilog expert to solve a bug on NetFPGA implementation of a modified Ethernet switch. It might be related with timing limitations of the Verilog code to gate conversion handling table writing and reading of MAC addresses at a table. More details on request.
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