Design a 3D-IC
I need help to design a 3D-IC consisting of 10 gates that have at least 3 TSVs by using Cadence tool.
1. Commented Verilog code for your design (code listing)
2. Verilog testbench for your code and results (code listing and output log file and screenshot )
3. Synthesized Verilog of your design from Synopsys Design Compiler (code listing and screenshot)
4. Chip layout of your design from Cadence Encounter Place & Route (screenshot)
- Verilog is a hardware description language (HDL) for developing and modeling circuits.
- The Cadence SimVision tool will help you simulate circuits that have been developed in Verilog.
- An RTL compiler takes an RTL version of a design (such as Verilog) and transforms (compiles) the RTL by mapping the design to components in a standard cell library (such as logic gates).
- Place and Route – Cadence Encounter
Looking to make some money?
- Set your budget and the time frame
- Outline your proposal
- Get paid for your work
Bids on this Project
Hardware & Software Design Solutions
I love engineering tasks. I have been in product design , development and testing area since past 37years. Wind and solar area are my preferred areas. I can take care of mathematical modeling , Programming in MATLAB, SIMULINK and LABView and real time programming as well as simulation Skills in MATLAB, FORTRAN,Pascal, C,C++, LABView, I have put minimum limits for project budgets: $42 for hourly consultation (that is, for 2 hours), and $45 for fix cost quotes for 2 hours of occupancy.
8 year's experience in digital system design using VHDL and verilog for FPGA's and CPLD's both for Xilinx and Altera Chips. I also have 8 years experience in working with Xilinx Ise form version 6.2 to 14.7 and Altera Quarus 2 for VHDL , verilog, system verilog and ip in addition to experience in Vivado design tool, and HLS and digital design using zynq7000
Efficiently handled Image Processing in MATLAB as well as on FPGA. Developed embedded applications using C.