verilog and designing small task

Budget $30 - $40 USD
Bids 6
Average Bid $396

Design a 3D-IC


I need help to design a 3D-IC consisting of 10 gates that have at least 3 TSVs by using Cadence tool.

Requirements:
1. Commented Verilog code for your design (code listing)
2. Verilog testbench for your code and results (code listing and output log file and screenshot )
3. Synthesized Verilog of your design from Synopsys Design Compiler (code listing and screenshot)
4. Chip layout of your design from Cadence Encounter Place & Route (screenshot)


Description:
- Verilog is a hardware description language (HDL) for developing and modeling circuits.
- The Cadence SimVision tool will help you simulate circuits that have been developed in Verilog.
- An RTL compiler takes an RTL version of a design (such as Verilog) and transforms (compiles) the RTL by mapping the design to components in a standard cell library (such as logic gates).
- Place and Route – Cadence Encounter



Thank you,

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