verilog and designing small task

This project received 6 bids from talented freelancers with an average bid price of $396 USD.

Get free quotes for a project like this
Employer working
Project Budget
$30 - $40 USD
Total Bids
Project Description

Design a 3D-IC

I need help to design a 3D-IC consisting of 10 gates that have at least 3 TSVs by using Cadence tool.

1. Commented Verilog code for your design (code listing)
2. Verilog testbench for your code and results (code listing and output log file and screenshot )
3. Synthesized Verilog of your design from Synopsys Design Compiler (code listing and screenshot)
4. Chip layout of your design from Cadence Encounter Place & Route (screenshot)

- Verilog is a hardware description language (HDL) for developing and modeling circuits.
- The Cadence SimVision tool will help you simulate circuits that have been developed in Verilog.
- An RTL compiler takes an RTL version of a design (such as Verilog) and transforms (compiles) the RTL by mapping the design to components in a standard cell library (such as logic gates).
- Place and Route – Cadence Encounter

Thank you,

Looking to make some money?

  • Set your budget and the timeframe
  • Outline your proposal
  • Get paid for your work

Hire Freelancers who also bid on this project

    • Forbes
    • The New York Times
    • Time
    • Wall Street Journal
    • Times Online