7 Segment driver in VHDL

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Project Description

Develop a packed BCD (two digit BCD) to dual seven segment display driver that will operate the dual display shown in the fig attached. The packed BCD input will be an 8-bit value, any unused input combinations should be handled appropriately. A user defined external clock may be used if required to drive the display multiplexing.
a) Using block diagrams, flowcharts, tables or any other design tool, design the system.
b) Implement the system in CPLD ( Xilinx coolrunnerII development board. Picture of the software is also attached). Include comments in your code to explain the operation program.
c) Test the program using the IDE simulator of the board mentioned above and record the test results including screen shots in a word document.

NB: The elements a, b and c are to be drawn together to form a formal report detailing the design, operation and test of the system designed

## Deliverables

1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.

2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables):
a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment.
b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request.
3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement).

## Platform


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