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Field Programmable Gate Array Implementation of Reed-Solomon

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Project Description

Abstract—This paper demonstrates an FPGA implementation

of the Reed-Solomon, RS(255,239), codec architecture for the

OTN G.709. The RS codec is designed to occupy the least

amount of logic blocks, be fast and parameterizable. I am

presenting an efficient implementation of the encoder algorithm

on reconfigurable devices in addition to a non-finalized version

of the decoder. Both encoder and decoder are synthesized to

Altera’s StratixII and benchmarks are run against Altera’s Reed

Solomon Code. Xelic’s encoder is measured to be about half the

size of Altera’s encoder. Effort on optimizing Xelic’s decoder is

underway to have an efficient implementation of the decoder

algorithm.

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