A 4 bit up/down modulo counter in VHDL. The main entity ( counter has 3 parts ) as shown in the .png file that is attached . The clock divider component takes the default clock signal at 50 MHz and reduces it to a 1 second signal . I have attached the clock divider code also, this is to be added as a component in the main file. The remaning two parts are the "counter" and the "4-bit modulo register", which are to be implemented as processes . Therefore, inside architecture, you will have 1 component and 2 processes. The modulo register (4 bit flip flop ) stores the value from the input pins whenever the system is reset, and sends this value(any value upto 15, since its only 4-bit) as the maximum count value to the counter In addition to enable and reset buttons, an additional "direction" button also comes into play. The counter counts up to the value sent from the modulo register if the direction button is not pressed ( direction=0), and counts down to 0 if the direction button is pressed. Also please generate a test bench file for this.
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I can do the project for you with in hours. Already have done more complicated programs than up down counters. So this is not a big deal. Feel free to message me.
I can produce the counter with test bench file as requested having 12 years experience of VHDL in industry and a MSc in Microelectronics Systems Design from Brunel University.