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Completed In4 days
1. Design a 2 to 4 decoder giving the truth table, Boolean equations and logic
Develop a Verilog module (structural) for the 2 to 4 decoder using
continuous assignment statements. Implement it using Xilinx’ WebPACK
and test it with ISim.
2. Develop an 8-bit 2 to 1 multiplexer with vectors to indicate the bus width.
Obtain a behavioral model of the multiplexer and implement it.
3. Design a 4 to 1 multiplexer using three 2 to 1 multiplexers using module
instantiation statements. Give the code and test results.
4. Draw a block diagram of an 8 to1 multiplexer using two 4 to 1 multiplexers
and one 2 to 1 multiplexer. Name the data and select inputs and also the
interconnections in the diagram.
Using Xilinx WebPACK and with the names for the ports as in the block
diagram develop an 8 to 1 multiplexer using two 4 to 1 module instances and
one 2 to 1 module instance. Show the code and test results. Program this on
a BASYS board and show the results.
(Note that in this problem module instances are used while in Pb.3 module
instantiation statements are used).
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